Abstract: The invention discloses methods of fabricating a semiconductor device structure having low source/drain junction capacitances and low junction leakage currents. The low source/drain junction capacitances are obtained by implementing in a self-aligned manner the major portions of the heavily-doped source and drain regions of a device over the trench-isolation region using highly-conductive silicided polycrystalline- or amorphous-semiconductor and the junction leakage currents resulting from the generation/recombination current in the depletion regions of the heavily-doped source and drain junctions due to the implant-induced defects can be much reduced or eliminated. Moreover, the contacts are made on the silicided heavily-doped source and drain regions over the trench-isolation regions, the traditional contact-induced leakage current due to the shallow source/drain junction can be completely eliminated by the present invention.

Abstract: A self-aligned multi-bit flash memory cell of the present invention comprises two floating-gate structures with a spacing dielectric layer being formed therebetween; a planarized control-gate layer over an intergate-dielectric layer being formed over the two floating-gate structures and the spacing dielectric layer; and a common-source/drain conductive bit line together with a first sidewall dielectric spacer being formed over a flat bed formed by a common-source/drain diffusion region and nearby etched raised field-oxide layers. A contactless multi-bit flash memory array of the present invention comprises a plurality of common-source/drain conductive bit lines being formed transversely to a plurality of parallel STI regions and a plurality of word lines integrated with a plurality of planarized control-gate layers of the described cells being patterned and formed transversely to the plurality of common-source/drain conductive bit lines.

Abstract: The dual-bit flash memory cells of the present invention include three regions: the gate region, the first-side region, and the second-side region. The gate region is formed between the first-side region and the second-side region and is defined by a masking photoresist step and is scalable. The gate region includes two stack-gate transistors formed in the side portions of the gate region with a select-gate transistor being formed therebetween for the first embodiment of the present invention and with a bit-line conductive island formed over a common-drain diffusion region for the second embodiment of the present invention. The first-side/second-side region includes a common-source conductive bus line being integrated with a conductive erasing anode for high-speed erasing. The cell size of each bit is smaller than 4F2.

Abstract: The trench-isolation structures for fabricating semiconductor devices using two different multilayer masking structures are disclosed by the present invention, in which the extended buffer spacers located in the isolation regions are formed on the sidewalls of two different multilayer masking structures having a masking dielectric layer on a pad-oxide layer and a masking dielectric layer on a conductive layer over a gate-oxide layer. The extended buffer spacers not only act as the etching mask for forming the trenches in the semiconductor substrate but also play significant roles for obtaining high-reliability and high-efficiency trench isolation of the present invention. The first role of the extended buffer spacers of the present invention is to offer the buffer regions for preventing the bird's beak formation around the edge of the active region during the thermal oxidation of the trench surface, so that the active area used to fabricate the active device is not sacrificed.

Abstract: An isolated stack-gate flash cell structure comprises a gate region being formed between common-source/drain regions. The common-source/drain region comprises a pair of divided source/drain diffusion regions being isolated by an etched-back planarized field-oxide layer formed over a shallow trench in a semiconductor substrate and a pair of extended floating-gate spacers being formed over a portion of a pair of etched-back first sidewall dielectric spacers and the etched-back planarized field-oxide layer. The gate region comprises a major floating-gate being formed over a tunneling dielectric layer and integrated with nearby two extended floating-gate spacers to form an integrated floating-gate. A word line over an intergate dielectric layer is formed over the integrated floating-gate. The isolated stack-gate flash cell structure is used to form two contactless parallel divided source/drain diffusion bit-lines arrays.

Abstract: A self-aligned split-gate flash memory cell and its contactless memory array are disclosed by the present invention, in which a floating-gate length and a control-gate length of a self-aligned split-gate flash memory cell are separately defined by two sidewall dielectric spacers being formed over the same sidewall on a common-source region and, therefore, can be controlled to be smaller than a minimum-feature-size of technology used; a contactless memory array comprises a plurality of common-source/drain conductive bus lines being formed alternately over the first/second flat beds; and a plurality of word lines together with the control-gates of a plurality of self-aligned split-gate flash memory cells being patterned and etched simultaneously by a set of hard masking layers are formed transversely to the plurality of common-source/drain conductive bus lines.

Abstract: A scalable stacked-gate flash memory device and its high-density memory arrays are disclosed by this invention. There are four different spacer techniques used to fabricate a scalable stacked-gate flash memory device: the first spacer technique is used to form the buffer-oxide spacers for implanting the channel stops of shallow-trench-isolation and oxidizing the etched surface of shallow trenches without sacrificing the active width of non-volatile semiconductor memory devices; the second spacer technique is used to highly adjust the coupling ratio of the self-aligned floating gate using a shallow-trench-isolation (STI) structure so that the applied control-gate voltage for programming and erase can be reduced; the third spacer technique is used to define the gate length of a scalable stacked-gate structure; and the fourth spacer technique is used to form the sidewall spacers for self-aligned source/drain implant, self-aligned source/drain or common buried-source silicidation, and self-aligned contacts.

Abstract: The scalable multi-bit flash memory cell includes three regions: the first-side region, the gate region, and the second-side region, in which the gate region includes two stack-gate transistors and one select-gate transistor. The first-side/second-side region comprises a sidewall-oxide spacer formed over the gate region and from top to bottom comprises a planarized thick-oxide layer, a silicided conductive layer formed on a flat bed, and a common-diffusion region. The stack-gate transistor comprises from top to bottom a sidewall dielectric spacer, an elongated control-gate layer formed over an intergate dielectric layer, and an integrated floating-gate layer. The select-gate transistor comprises a planarized conductive island formed over a gate-dielectric layer and is connected to a word line. A plurality of scalable multi-bit flash memory cells are alternately arranged to form a scalable multi-bit flash memory cell array.

Abstract: The scalable multi-bit flash memory cell includes three regions: the first-side region, the gate region, and the second-side region, in which the gate region includes two stack-gate transistors and one select-gate transistor. The first-side/second-side region comprises a sidewall-oxide spacer formed over the gate region and from top to bottom comprises a planarized thick-oxide layer, a silicided conductive layer formed on a flat bed, and a common-diffusion region. The stack-gate transistor comprises from top to bottom a sidewall dielectric spacer, an elongated control-gate layer formed over an intergate dielectric layer, and an integrated floating-gate layer. The select-gate transistor comprises a planarized conductive island formed over a gate-dielectric layer and is connected to a word line. A plurality of scalable multi-bit flash memory cells are alternately arranged to form a scalable multi-bit flash memory cell array.

Abstract: Methods of fabricating a stack-gate flash memory array are disclosed by the present invention, in which a self-aligned integrated floating-gate layer includes a major floating-gate layer formed on a thin tunneling dielectric layer and two extended floating-gate layers formed on planarized filed-oxides (FOX); a high-conductivity word line is formed by a composite conductive layer of metal or silicide/barrier-metal/doped polycrystalline- or amorphous-silicon as a control-gate layer and is encapsulated by the dielectric layers; a self-registered common-source/drain bus line is formed on a flat bed formed by common-source/drain diffusion regions and planarized field-oxides; a self-registered common-source/drain landing island is formed on a common-source/drain diffusion region to act as a self-aligned contact and a dopant diffusion source for forming a shallow heavily-doped commmon-source/drain diffusion region.

Abstract: The dual-bit flash memory cells of the present invention include three regions: the gate region, the first-side region, and the second-side region. The gate region is formed between the first-side region and the second-side region and is defined by a masking photoresist step and is scalable. The gate region comprises two stack-gate transistors formed in the side portions of the gate region with a select-gate transistor being formed therebetween for the first embodiment of the present invention and with a bit-line conductive island formed over a common-drain diffusion region for the second embodiment of the present invention. The first-side/second-side region comprises a common-source conductive bus line being integrated with a conductive erasing anode for high-speed erasing. The cell size of each bit is smaller than 4F2.

Abstract: A contactless NOR-type memory array of the present invention comprises a plurality of integrated floating-gate layers formed on a shallow-trench isolation structure, a plurality of word lines having an interlayer dielectric layer formed on an elongated control-gate layer for each word line, a plurality of common-source bus lines having a silicided conductive layer formed over a flat bed for each common-source line and, a plurality of bit lines with each bit line being integrated with a plurality of silicided conductive islands formed on the common-drain diffusion regions. The contactless NOR-type memory array of the present invention may offer: a cell size of 4F2, no contact problems for shallow source/drain junction of the cell, lower common-source bus line resistance and capacitance, and better density*speed*power product as compared to existing NAND-type memory array.

Abstract: A scalable stack-gate flash memory cell and its contactless memory array are disclosed by the present invention, in which the control-gate length and the implanted region of a scalable stack-gate flash memory cell are separately defined by two sidewall dielectric spacers formed over a sidewall on the common-source region and, therefore, can be controlled to be smaller than a minimum-feature-size of technology used; a contactless memory array comprises a plurality of common-source/drain conductive bus lines being formed alternately over the flat beds and a plurality of word lines together with the control-gates of scalable stack-gate flash memory cells being patterned and etched simultaneously by a set of hard masking layers are formed transversely to the plurality of common-source/drain conductive bus lines.

Abstract: A self-aligned split-gate flash memory cell and its contactless NOR-type memory array are disclosed by the present invention, which comprise a shallow-trench-isolation structure having an integrated floating-gate structure and the embedded double-sides erase cathodes; a self-aligned split-gate flash memory cell having a steep or one-side tapered floating-gate structure; a bit line integrated with planarized common-drain conductive islands; and a common-source conductive bus line. Therefore, the present invention offers a smaller cell area, a higher coupling ratio through an integrated floating-gate structure, a higher erasing speed through the embedded double-sides erase cathodes, higher contact integrity for shallow junction through a common-drain conductive island, and lower bus-line resistance and capacitance through a common-source conductive bus line.

Abstract: A scalable vertical DRAM cell structure comprising a scalable trench region and a self-aligned common-drain diffusion region are disclosed by the present invention, in which the scalable trench region comprises a deep-trench region having a vertical transistor and a second-type STI region being defined by a spacer technique. The scalable vertical DRAM cell structure can offer a DARM cell size equal to or smaller than 4F2 and is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands over common-gate conductive connector islands and a plurality of common-drain conductive bit-lines.

Abstract: A scalable split-gate flash memory cell structure of the present invention comprises a common-source region, a scalable split-gate region being formed by a sidewall dielectric spacer, and a scalable common-drain region, wherein the scalable split-gate region comprising a floating-gate region being defined by another sidewall dielectric spacer has a tip-cathode line for erasing. The cell size of the present invention is scalable and can be made to be equal to 4F2 or smaller. The scalable split-gate flash memory cell structure is used to implement two contactless flash memory arrays: a contactless NOR-type flash memory array and a contactless parallel common-source/drain conductive bit-lines flash memory array for high speed read/write/erase operations. Moreover, the contactless flash memory arrays can be fabricated with less critical masking steps as compared to the prior art.

Abstract: A self-aligned split-gate flash memory cell of the present invention comprises an integrated floating-gate layer being at least formed on a first gate-dielectric layer having a first intergate-dielectric layer formed on its top and a second intergate-dielectric layer formed on its inner sidewall; a planarized control/select-gate layer being at least formed on a second gate-dielectric layer and the first second intergate-dielectric layers; a common-source and a common-drain diffusion regions; and an integrated source-side erase structure being at least formed on a portion of the common-source diffusion region and on a tunneling-dielectric layer formed over an outer sidewall of the integrated floating-gate layer. The self-aligned split-gate flash memory cells are configured into two contactless array architectures: a contactless NOR-type array and a contactless parallel common-source/drain conductive bit-lines array.

Abstract: A self-aligned split-gate flash memory cell of the present invention comprises a planarized control/select-gate conductive layer having a portion formed at least on a second gate-dielectric layer and another portion formed at least on a single-side tip-shaped floating-gate structure being formed on a first gate-dielectric layer, wherein a dielectric layer is formed over the single-side tip-shaped floating-gate structure to act as a first intergate-dielectric layer and a second intergate-dielectric layer is formed over an inner sidewall of the single-side tip-shaped floating-gate structure. The self-aligned split-gate flash memory cell is configured into two contactless array architectures: a contactless NOR-type flash memory array and a contactless parallel common-source/drain conductive bit-lines flash memory array.

Abstract: A self-aligned split-gate flash memory cell of the present invention comprises a single-side dish-shaped floating-gate structure being formed on a first gate-dielectric layer with a first intergate-dielectric layer being formed on its top portion and a second intergate-dielectric layer being formed on its inner sidewall and tip portion; a planarized control/select-gate conductive layer being at least formed over a second gate-dielectric layer and the first/second intergate-dielectric layers; and a common-source diffusion region and a common-drain diffusion region being implanted by aligning to the planarized control/select-gate conductive layer. The self-aligned split-gate flash memory cells are configured into two contactless array architectures: a contactless NOR-type flash memory array and a contactless parallel common-source/drain conductive bit-lines flash memory array.

Abstract: A scaled stack-gate non-volatile semiconductor memory device having atapered floating-gate structure is disclosed by the present invention, in which a stack-gate structure including a masking dielectric layer over a control-gate layer over an intergate dielectric layer over a tapered floating-gate layer on a thin tunneling-dielectric layer is formed on a semiconductor substrate having an active region isolated by field-oxides and is oxidized. A deeper double-diffused source region having a graded doping profile formed near a gate edge and a shallow drain diffusion region are formed as the first embodiment of the present invention. The deeper double-diffused source and drain regions having a graded doping profile formed near two gate edges are formed as the second embodiment of the present invention. The shallower double-diffused source and drain regions having a graded doping profile formed near two gate edges are formed as the third embodiment of the present invention.