Abstract: A vertical DRAM cell structure is disclosed by the present invention, in which a trench structure comprises a deep-trench region having a vertical transistor and a second-type STI region being formed in a side portion of the deep-trench region and a common-drain structure comprises different implant regions under a common-drain diffusion region being formed in another side portion of the deep-trench region. The vertical DRAM cell structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common-drain conductive bit-lines.

Abstract: A vertical transistor DRAM structure is disclosed by the present invention, in which a trench structure comprises a deep-trench region having a vertical transistor and a second-type shallow-trench-isolation region being formed in a side portion of the deep-trench region and a common-drain structure comprises different implant regions being formed under a common-drain diffusion region in another side portion of the deep-trench region. The vertical transistor DRAM structure is, used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated. with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common-drain conductive bit-lines.

Abstract: The nanometer-gate MOSFET device of the present invention comprises a shallow-trench-isolation structure; a pair of second conductive sidewall spacers being formed over each inner sidewall of a gate region and on a portion of a first conductive layer and a first raised field-oxide layers for forming an implant region in a central portion of a channel; a buffer-oxide layer being formed over each sidewall of the gate region for forming lightly-doped source/drain diffusion regions; a first sidewall dielectric spacer being formed over each sidewall of the buffer-oxide layers for forming heavily-doped source/drain diffusion regions; a second sidewall dielectric spacer being formed over each sidewall of the first sidewall dielectric spacers for forming a metal-silicide layer over each of heavily-doped source/drain diffusion regions; and a highly conductive-gate structure being formed in the gate region.

Abstract: A self-aligned split-gate flash cell structure of the present invention comprises a ridge-shaped floating-gate layer being formed on a first gate dielectric layer with a first intergate dielectric layer being formed on its top portion and a second intergate dielectric layer being formed on its inner sidewall; a control/select-gate conductive layer being formed at least over a second gate dielectric layer and the first/second intergate dielectric layers; and a common-source diffusion region and a common-drain diffusion region being implanted by aligning to the control/select-gate conductive layer. The self-aligned split-gate flash cell structure is configured into two contactless array architectures: a contactless NOR-type flash memory array and a contactless parallel common-source/drain conductive bit-lines flash memory array.

Abstract: The scalable stack-type DRAM memory structure of the present invention comprises a scalable DRAM transistor structure and a scalable DRAM capacitor structure. The scalable DRAM transistor structure comprises a plurality of transistor-stacks, a plurality of common-drain regions, and a plurality of source regions being formed over a shallow-trench-isolation structure without a dummy-transistor structure by using a spacer-formation technique. The scalable DRAM capacitor structure comprises a plurality of rectangular tube-shaped cavities being formed over thin fourth conductive islands to form a high-capacity DRAM capacitor for each of DRAM cells; and a plurality of planarized conductive contact-islands over planarized third conductive islands being patterned and simultaneously etched with a plurality of bit-lines for forming a contactless DRAM memory. The cell size of a DRAM cell is scalable and can be made to be smaller than 6F2.

Abstract: A vertical DRAM cell structure is disclosed by the present invention, in which a trench structure comprises a deep-trench region having a vertical transistor and a second-type STI region being formed in a side portion of the deep-trench region and a common-drain structure comprises different implant regions under a common-drain diffusion region being formed in another side portion of the deep-trench region. The vertical DRAM cell structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common- drain conductive bit-lines.

Abstract: A self-aligned lateral-transistor DRAM cell structure is disclosed by the present invention, in which a trench structure comprises a trench region and a trench-isolation region being formed in a side portion of the trench region and a self-aligned lateral-transistor structure comprises a merged common-source diffusion region, a self-aligned gate-stack region, and a self-aligned common-drain diffusion region being formed in another side portion of the trench region by using spacer-formation techniques. The unit cell size of the self-aligned lateral-transistor DRAM cell structure can be fabricated to be equal to 6F2 or smaller. The self-aligned lateral-transistor DRAM cell structure is used to implement two contactless DRAM arrays for high-speed read and write operations.

Abstract: A contactless NOR-type memory array of the present invention comprises a plurality of integrated floating-gate layers formed on a shallow-trench isolation structure, a plurality of word lines having an interlayer dielectric layer formed on an elongated control-gate layer for each word line, a plurality of common-source bus lines having a silicided conductive layer formed over a flat bed for each common-source line and, a plurality of bit lines with each bit line being integrated with a plurality of silicided conductive islands formed on the common-drain diffusion regions. The contactless NOR-type memory array of the present invention offers a cell size of 4F2, no contact problems for shallow source/drain junction of the cell, lower common-source bus line resistance and capacitance, and better density*speed*power product as compared to existing NAND-type memory array.

Abstract: A self-aligned vertical transistor DRAM structure comprising a self-aligned trench structure and a self-aligned common-drain structure are disclosed by the present invention, in which the self-aligned trench structure comprises a deep-trench capacitor region having a vertical transistor and a second-type shallow-trench-isolation region being defined by a spacer technique and the self-aligned common-drain structure comprises a common-drain region being defined by another spacer technique. The self-aligned vertical transistor DRAM structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common-drain conductive bit-lines.

Abstract: A self-aligned vertical transistor DRAM structure comprising a self-aligned trench structure and a self-aligned common-drain structure are disclosed by the present invention, in which the self-aligned trench structure comprises a deep-trench capacitor region having a vertical transistor and a second-type shallow-trench-isolation region being defined by a spacer technique and the self-aligned common-drain structure comprises a common-drain region being defined by another spacer technique. The self-aligned vertical transistor DRAM structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common-drain conductive bit-lines.

Abstract: A vertical transistor DRAM structure is disclosed by the present invention, in which a trench structure comprises a deep-trench region having a vertical transistor and a second-type shallow-trench-isolation region being formed in a side portion of the deep-trench region and a common-drain structure comprises different implant regions being formed under a common-drain diffusion region in another side portion of the deep-trench region. The vertical transistor DRAM structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common- drain conductive bit-lines.

Abstract: A self-aligned trench-type DRAM structure comprising a self-aligned DRAM capacitor structure and a self-aligned DRAM transistor structure are disclosed by the present invention, in which the self-aligned DRAM capacitor structure comprises a deep-trench capacitor region and a shallow-trench-isolation region being defined by a spacer technique and the self-aligned DRAM transistor structure comprises a scalable gate-stack region and a common-drain region being defined by another spacer technique. The self-aligned trench-type DRAM structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized conductive-gate islands and a plurality of common-drain conductive bit-lines.

Abstract: A self-aligned multi-bit flash memory cell of the present invention comprises two floating-gate structures with a spacing dielectric layer being formed therebetween; a planarized control-gate layer over an intergate-dielectric layer being formed over the two floating-gate structures and the spacing dielectric layer; and a common-source/drain conductive bit line together with a first sidewall dielectric spacer being formed over a flat bed formed by a common-source/drain diffusion region and nearby etched raised field-oxide layers. A contact less multi-bit flash memory array of the present invention comprises a plurality of common-source/drain conductive bit lines being formed transversely to a plurality of parallel STI regions and a plurality of word lines integrated with a plurality of planarized control-gate layers of the described cells being patterned and formed transversely to the plurality of common-source/drain conductive bit lines.

Abstract: Methods of fabricating a stack-gate flash memory array are disclosed by the present invention, in which a self-aligned integrated floating-gate layer includes a major floating-gate layer formed on a thin tunneling dielectric layer and two extended floating-gate layers formed on planarized filed-oxides (FOX); a high-conductivity word line is formed by a composite conductive layer of metal or silicide/barrier-metal/doped polycrystalline- or amorphous-silicon as a control-gate layer and is encapsulated by the dielectric layers; a self-registered common-source/drain bus line is formed on a flat bed formed by common-source/drain diffusion regions and planarized field-oxides; a self-registered common-source/drain landing island is formed on a common-source/drain diffusion region to act as a self-aligned contact and a dopant diffusion source for forming a shallow heavily-doped commmon-source/drain diffusion region.

Abstract: The scalable stack-type DRAM memory structure of the present invention comprises a scalable DRAM transistor structure and a scalable DRAM capacitor structure. The scalable DRAM transistor structure comprises a plurality of transistor-stacks, a plurality of common-drain regions, and a plurality of source regions being formed over a shallow-trench-isolation structure without a dummy-transistor structure by using a spacer-formation technique. The scalable DRAM capacitor structure comprises a plurality of rectangular tube-shaped cavities being formed over thin fourth conductive islands to form a high-capacity DRAM capacitor for each of DRAM cells; and a plurality of planarized conductive contact-islands over planarized third conductive islands being patterned and simultaneously etched with a plurality of bit-lines for forming a contactless DRAM memory. The cell size of a DRAM cell is scalable and can be made to be smaller than 6F2.

Abstract: The stack-type DRAM memory structure of the present invention comprises a plurality of self-aligned thin third conductive islands over shallow heavily-doped source diffusion regions without dummy transistors to obtain a cell size of 6F2 or smaller; a rectangular tube-shaped cavity having a conductive island formed above a nearby transistor-stack being formed over each of the self-aligned thin third conductive islands to offer a larger surface area for forming a high-capacity DRAM capacitor of the present invention; a planarized third conductive island being formed between a pair of first sidewall dielectric spacers and on each of shallow heavily-doped common-drain diffusion regions to offer a larger contact area and a higher contact integrity; and a plurality of planarized conductive contact-islands being formed over the planarized third conductive islands to eliminate the aspect-ratio effect and being patterned and etched simultaneously with a plurality of bit lines.

Abstract: A scaled MOSFET device of the present invention comprises a shallow-trench-isolation structure being formed on a semiconductor substrate; a conductive-gate structure having a pair of second conductive sidewall spacers formed over each inner sidewall of a gate region and on a first conductive layer and first raised field-oxide layers for forming an implant region in a central portion of a channel and a planarized third conductive layer for forming a salicide-gate structure or a polycide-gate structure; a buffer-dielectric layer being formed over each sidewall of the conductive-gate structure for forming lightly-doped source/drain diffusion regions; a first sidewall dielectric spacer being formed over each sidewall of the buffer-dielectric layers for forming heavily-doped source/drain diffusion regions; and a second sidewall dielectric spacer being formed over each sidewall of the first sidewall dielectric spacers for forming a self-aligned silicidation contact over each of the heavily-doped source/drain diffus

Abstract: The nanometer-gate MOSFET device of the present invention comprises a shallow-trench-isolation structure; a pair of second conductive sidewall spacers being formed over each inner sidewall of a gate region and on a portion of a first conductive layer and a first raised field-oxide layers for forming an implant region in a central portion of a channel; a buffer-oxide layer being formed over each sidewall of the gate region for forming lightly-doped source/drain diffusion regions; a first sidewall dielectric spacer being formed over each sidewall of the buffer-oxide layers for forming heavily-doped source/drain diffusion regions; a second sidewall dielectric spacer being formed over each sidewall of the first sidewall dielectric spacers for forming a metal-silicide layer over each of heavily-doped source/drain diffusion regions; and a highly conductive-gate structure being formed in the gate region.

Abstract: A self-aligned split-gate flash memory cell and its contactless memory array in which a floating-gate length and a control-gate length of a self-aligned split-gate flash memory cell are separately defined by two sidewall dielectric spacers being formed over the same sidewall on a common-source region and, therefore, can be controlled to be smaller than a minimum-feature-size of technology used; a contactless memory array includes a plurality of common-source/drain conductive bus lines being formed alternately over the first/second flat beds; and a plurality of word lines together with the control-gates of a plurality of self-aligned split-gate flash memory cells being patterned and etched simultaneously by a set of hard masking layers are formed transversely to the plurality of common-source/drain conductive bus lines.

Abstract: A stack-gate non-volatile memory device with a tapered floating-gate structure is disclosed by the present invention, in which the tapered floating-gate structure offers a longer effective channel length to alleviate the punch-through effect and a larger surface area for erasing or programming between the tapered floating-gate structure and the integrated common-source/drain conductive structure. The stack-gate non-volatile memory devices of the present invention are implemented into three contactless array architectures: a contactless NOR-type array, a contacless NAND-type array, and a contactless parallel common-source/drain conductive bit-lines array. The features and advantages of the contactless memory arrays are a smaller cell size of 4F2, a smaller common-source/drain bus-line resistance and capacitance, a higher erasing speed, and a smaller bit/word-line resistance and capacitance, as compared to the prior arts.