Abstract: A voltage regulator circuit includes a first amplifier, a second amplifier and a transistor. Respective first input terminals of the first and second amplifiers are coupled to a first reference voltage and a second reference voltage, respectively. A connection terminal of the transistor is coupled to a supply voltage. A control terminal of the transistor is selectively coupled to one of respective output terminals of the first and second amplifiers. When the control terminal of the transistor is coupled to the output terminal of the first amplifier, another connection terminal of the transistor is coupled to a second input terminal of the first amplifier to output a regulated voltage. When the control terminal of the transistor is coupled to the output terminal of the second amplifier, the another connection terminal of the transistor is coupled to a second input terminal of the second amplifier to output the regulated voltage.

Abstract: A class-D amplifier includes a loop filter configured to receive first and second feedback signals, to receive first and second input signals through first and second resistors respectively, and to filter the first and second input signals and the first and second feedback signals to generate first and second filtered signals; a triangle wave generator configured to generate a triangle wave according to first and second reference voltages; first and second comparators configured to compare the first and second filtered signals with the triangle wave respectively to generate the first and second pulse width modulation (PWM) signals, respectively; first and second driver circuits configured to generate first and second output signals according to the first and second PWM signals, respectively; and a reference voltage generation circuit configured to generate the first and second reference voltages according to a control signal.

Abstract: A connector includes an insulating housing, at least one terminal set, and a latch member. The insulating housing includes a latch panel, a first part, a second part, a latching portion, and a guiding portion. The latch panel has a first surface and a second surface opposite to each other, and a latch opening is communicated with the first surface and the second surface. The first part is connected to the first surface and has at least one slot. The second part is connected to the second surface. The guiding portion is connected to the second surface. The terminal set is disposed in the slot. The latch member includes an actuating portion and a latch arm. The latch arm is connected to the actuating portion and is slidably engaged with the guiding portion and partially passes through the first surface via the latch opening.

Abstract: A voltage regulator circuit includes a first amplifier, a second amplifier and a transistor. Respective first input terminals of the first and second amplifiers are coupled to a first reference voltage and a second reference voltage, respectively. A connection terminal of the transistor is coupled to a supply voltage. A control terminal of the transistor is selectively coupled to one of respective output terminals of the first and second amplifiers. When the control terminal of the transistor is coupled to the output terminal of the first amplifier, another connection terminal of the transistor is coupled to a second input terminal of the first amplifier to output a regulated voltage. When the control terminal of the transistor is coupled to the output terminal of the second amplifier, the another connection terminal of the transistor is coupled to a second input terminal of the second amplifier to output the regulated voltage.

Abstract: A connector assembly includes a first connector and a second connector coupled to the first connector. The first connector includes a first bottom plate, first side plates, and a first conductive terminal. The first side plates and the first bottom plate jointly define an accommodating space. The first conductive terminal passes through the first bottom plate and extends in the accommodating space. The second connector includes a second bottom plate, second side plates, and a second conductive terminal. The second plates and the second bottom plate form at least one cavity. The second conductive terminal is located in the at least one cavity. The second conductive terminal includes a contacting portion and a connecting portion connected to the contacting portion. The contacting portion has a hollowed portion. The first conductive terminal enters the hollowed portion and is electrically connected to the second conductive terminal.

Abstract: The present invention relates to an expression system and a method ensuring constant-level concentration of an output. The invention also relates to a cell comprising the expression system.

Abstract: A connector includes a housing, a first conductive terminal set, and a second conductive terminal set. The housing includes a bottom portion, two upright portions, two wing portions, a limiting portion, an extending portion, and a latch. The two upright portions extend in parallel from the bottom portion. The two upright portions jointly define a trench. The extending portion extends from a side surface of the bottom portion and is connected to one of the two wing portions. The extending portion has a latch channel. The wing portion has a through hole and communicates with the latch channel. A latch is slidably accommodated in the latch channel and is configured to partially pass through the through hole. The first conductive terminal set and the second conductive terminal set are accommodated in an accommodating space of the housing and respectively extend adjacent to the two upright portions.

Abstract: The present disclosure discloses an oscillating circuit having a temperature compensation mechanism. A NAND gate receives an input signal transiting from a low state level to a maintaining high state to initialize an oscillating behavior and a delayed control signal to generate an output oscillating signal. A first inverter having a negative temperature coefficient resistance inverts the output oscillating signal to generate an inverted output oscillating signal to be received and delayed by a RC delay circuit, including an oscillating resistor having a positive temperature coefficient resistance and an oscillating capacitor to generate a delayed and inverted control signal. A second inverter inverts the delayed and inverted control signal to generate a delayed control signal. A third inverter inverts the output oscillating signal to generate a final oscillating signal.

Abstract: A connector assembly includes a first connector, a second connector, and a first plug. The first connector includes a first housing, a conductive terminal, and a first engaging structure. The first housing has a chamber. The conductive terminal includes a cylindrical structure partially located in the chamber. The first engaging structure is disposed on an outer surface of the first housing. The two connectors can be coupled along a mating direction. The second connector includes a second housing, a busbar terminal, and a second engaging structure. The second housing is able to be partially accommodated in the chamber. The second housing has a channel and a positioning slot communicating with the channel. The busbar terminal is located in the channel of the second housing. The second engaging structure is engaged with the first engaging structure. The first plug is located in the positioning slot.

Abstract: An electrical connector includes: a longitudinal housing defining a longitudinal direction and a front-rear direction perpendicular to the longitudinal direction; a row of terminals including signal terminals and grounding terminals; and a grounding member retained in the housing and having plural first fingers and plural second fingers, wherein each of the first fingers extends in the longitudinal direction, each of the second fingers extends in the front-rear direction, and each grounding terminal is mechanically and electrically connected with a corresponding first finger and a corresponding second finger.

Abstract: A connector assembly includes a busbar connector, a first cable-end connector, a second cable-end connector, a first cable, and a second cable. The first cable-end connector is electrically connected to the busbar connector. The second cable-end connector is electrically connected to the busbar connector. The first cable is connected between the busbar connector and the first cable-end connector. The second cable is connected between the busbar connector and the second cable-end connector. A length of the first cable is different from a length of the second cable.

Abstract: An audio amplification system includes a filter circuit, a signal generation circuit, a waveform conversion circuit, a driving circuit, and a control circuit. The filter circuit is configured to generate a filtered signal according to an audio input signal, an audio output signal and a filter bandwidth. The signal generation circuit is configured to generate an oscillation signal with an oscillation frequency. The waveform conversion circuit is configured to generate a pulse-width modulation signal according to the filtered signal and the oscillation signal. The driving circuit is configured to generate the audio output signal according to the pulse-width modulation signal. The control circuit is configured to dynamically adjust the filter bandwidth and the oscillation frequency according to a digital control code. The digital control code and the audio input signal are respectively related to audio input amplitude.

Abstract: A phase-locked loop circuit includes a phase frequency detector (PFD) circuit, a digital code generator circuit, a frequency divider and an oscillator circuit. The PFD circuit is configured to detect a difference in phase and frequency between a reference clock and a feedback clock to generate a first control signal and a second control signal. The digital code generator circuit is configured to process the second control signal to generate a digital code. The frequency divider is configured to receive an output clock to generate the feedback clock. The oscillator circuit is configured to generate the output clock according to the first control signal and the digital code. A frequency of the output clock is determined according to a first control parameter and a second control parameter of different types. The first and second control parameters are adjusted in response to the first control signal and the digital code respectively.

Abstract: A phase-locked loop circuit includes a phase frequency detector (PFD) circuit, a digital code generator circuit, a frequency divider and an oscillator circuit. The PFD circuit is configured to detect a difference in phase and frequency between a reference clock and a feedback clock to generate a first control signal and a second control signal. The digital code generator circuit is configured to process the second control signal to generate a digital code. The frequency divider is configured to receive an output clock to generate the feedback clock. The oscillator circuit is configured to generate the output clock according to the first control signal and the digital code. A frequency of the output clock is determined according to a first control parameter and a second control parameter of different types. The first and second control parameters are adjusted in response to the first control signal and the digital code respectively.

Abstract: An integrated circuit in a transmitter includes a multi-lane interface, N signal generating circuits, a lane selection circuit and a control circuit. The multi-lane interface has N lanes. M of the N signal generating circuits are configured to generate M clock signals respectively. (N-M) of the N signal generating circuits are configured to generate (N-M) data signals respectively. The lane selection circuit is configured to select M of the N lanes as M clock lanes by coupling the M clock signals to the M clock lanes respectively, and couple one of the (N-M) data signals to one of remaining (N-M) lanes, serving as (N-M) data lanes, according to a data select signal. The control circuit is configured to generate a data select signal according to a lane identifier of the one of the (N-M) lanes. The data select signal has a signal value mapping to the lane identifier.

Abstract: A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit.

Abstract: A current transmission assembly and a current transmission system are provided. The current transmission system includes the current transmission assembly and a circuit board structure. The current transmission assembly includes a pluggable component, at least one conductor component, and at least one electrically connecting component. The pluggable component includes a housing, at least one set of electrically conductive arms, and at least one connecting member. The at least one sets of electrically conductive arms is disposed inside the housing. The at least one conductor component includes an electrical insulator and a wire main body. The electrical insulator encircles the wire main body, so that a first terminal and a second terminal are exposed from the wire main body, and the first terminal is connected to the at least one two connecting member.

Abstract: A voltage regulator circuit includes a first amplifier, a second amplifier and a transistor. Respective first input terminals of the first and second amplifiers are coupled to a first reference voltage and a second reference voltage, respectively. A connection terminal of the transistor is coupled to a supply voltage. A control terminal of the transistor is selectively coupled to one of respective output terminals of the first and second amplifiers. When the control terminal of the transistor is coupled to the output terminal of the first amplifier, another connection terminal of the transistor is coupled to a second input terminal of the first amplifier to output a regulated voltage. When the control terminal of the transistor is coupled to the output terminal of the second amplifier, the another connection terminal of the transistor is coupled to a second input terminal of the second amplifier to output the regulated voltage.

Abstract: A phase-locked loop circuit includes a phase frequency detector (PFD) circuit, a digital code generator circuit, a frequency divider and an oscillator circuit. The PFD circuit is configured to detect a difference in phase and frequency between a reference clock and a feedback clock to generate a first control signal and a second control signal. The digital code generator circuit is configured to process the second control signal to generate a digital code. The frequency divider is configured to receive an output clock to generate the feedback clock. The oscillator circuit is configured to generate the output clock according to the first control signal and the digital code. A frequency of the output clock is determined according to a first control parameter and a second control parameter of different types. The first and second control parameters are adjusted in response to the first control signal and the digital code respectively.

Abstract: A voltage regulator circuit includes a first amplifier, a second amplifier and a transistor. Respective first input terminals of the first and second amplifiers are coupled to a first reference voltage and a second reference voltage, respectively. A connection terminal of the transistor is coupled to a supply voltage. A control terminal of the transistor is selectively coupled to one of respective output terminals of the first and second amplifiers. When the control terminal of the transistor is coupled to the output terminal of the first amplifier, another connection terminal of the transistor is coupled to a second input terminal of the first amplifier to output a regulated voltage. When the control terminal of the transistor is coupled to the output terminal of the second amplifier, the another connection terminal of the transistor is coupled to a second input terminal of the second amplifier to output the regulated voltage.