Abstract: The invention refers to a light emitting device including a semiconductor chip having a main radiation surface, which emits UV light in operation, a phosphor, which is arranged in the radiation beam of the UV light, absorbs partially the UV light, wherein the phosphor converts the UV light into visible light so that the device emits mixed light comprising the UV light as well as visible light.

Abstract: A chip structure is provided. The chip structure includes: a first lower chip structure; and an upper chip structure on the first lower chip structure and having a pixel array region. The first lower chip structure includes: a first lower semiconductor substrate having a first side and a second side opposing each other; a first portion on the first side of the first lower semiconductor substrate; and a second portion on the second side of the first lower semiconductor substrate, the first portion of the first lower chip structure includes a gate wiring, the second portion of the first lower chip structure includes a second side wiring and a heating element, and the heating element is on the same plane as that of the second side wiring and has a length greater than that of the second side wiring.

Abstract: In a method of manufacturing a stack package, a first semiconductor chip is formed on a first package substrate. A second semiconductor chip is formed on a second package substrate. A plurality of signal pads and a thermal diffusion member are formed on a lower surface and/or an upper surface of an interposer substrate, the signal pad having a first height and the thermal diffusion member having a second height greater than the first height. The first package substrate, the interposer substrate, and the second package substrate are sequentially stacked on one another such that the thermal diffusion member is in contact with an upper surface of the first semiconductor chip or a lower surface of the second package substrate.

Abstract: An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.

Abstract: A sensor element is disclosed.

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.

Abstract: A low-shock separation device is characterized in that an internal locking structure is unlocked and a bolt is separated by operating a specific part of components thereof using high pressure that is generated by combustion of powder.

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.

Abstract: The present invention relates to a rotating inspector for a camera module. The rotating inspector includes a rotary table having one or more socket units on which the camera module mounted; a plurality of inspection devices disposed around the rotary table to inspect the camera module; test boards disposed on the rotary table, each of test boards being connected to the one or more socket units, respectively to control the camera module and generate inspection data for the camera module; a first data processing unit disposed on the rotary table and analyzing the inspection data to generate result data for possible defects of the camera module; a second data processing unit disposed outside the rotary table, the second data processing unit being configured to receive the result data and to sort and store the received data; and a data transmission unit transmitting the result data generated in the first data processing unit to the second data processing unit.

Abstract: The present disclosure is an acryl film formed from a main dope solution including an acryl resin shown in the following formula 1 and CSR particles, and peel strength measured in peeling speed of 0.5 mpm is 20 gf/2 inch or less, tear strength is 6 gf or more, has excellent peel strength, thereby visual stain by thickness unevenness is improved, and having excellent tear strength and good brittleness. a and b are an integer and 1 or more. MMA-BMA wherein, MMA is methyl methacrylate unit and BMA is butyl methacrylate unit.

Abstract: A semiconductor package is provided which includes a redistribution substrate, an interconnect substrate on the redistribution substrate, a metal layer on the semiconductor chip, a semiconductor chip on the redistribution substrate and in the hole of the interconnect substrate, and a mold layer in a gap between the semiconductor chip and the interconnect substrate. The interconnect substrate includes a hole penetrating thereinside. The interconnect substrate includes base layers and a conductive member extending through the base layers. A top surface of the interconnect substrate is positioned either above or below the level of the top surface of the metal layer.

Abstract: A heat radiation device includes a semiconductor substrate. A first electrode is disposed on the semiconductor substrate. A second electrode is disposed on the semiconductor substrate and is spaced apart from the first electrode. A first through electrode is disposed in the semiconductor substrate. The first through electrode is electrically connected to the first electrode.

Abstract: A low-shock separation device is characterized in that an internal locking structure is unlocked and a bolt is separated by operating a specific part of components thereof using high pressure that is generated by combustion of powder.

Abstract: Disclosed is a light-material coupling and emitting apparatus for coupling and emitting light and a material. The present disclosure is to utilize light coupled with a gaseous material or a certain state of material. According to the present disclosure, light is coupled with a gas, a liquid, or any state (plasma state) of material, and the coupled light and the material are emitted toward a target object or a predetermined region. When reaching the target object or the predetermined region, the material reacts with another material existing around the target object or the predetermined region. According to one embodiment, when light coupled with a first material is emitted from the light-material coupling and emitting apparatus, the first material coupled with the light falls away from the light and then chemically reacts with a second material. The apparatus uses a specific effect caused by this chemical reaction.

Abstract: A semiconductor package includes a semiconductor chip having a first surface that is an active surface and a second surface opposing the first surface, a first redistribution portion disposed on the first surface, the first redistribution portion including a lower wiring layer electrically connected to the semiconductor chip, a thermal conductive layer disposed on the second surface of the semiconductor chip, a sealing layer surrounding a side surface of the semiconductor chip and a side surface of the thermal conductive layer, and a second redistribution portion disposed on the sealing layer, the second redistribution portion including a first upper wiring layer connected to the thermal conductive layer, the second redistribution portion including a second upper wiring layer electrically connected to the semiconductor chip.

Abstract: A semiconductor package is provided which includes a redistribution substrate, an interconnect substrate on the redistribution substrate, a metal layer on the semiconductor chip, a semiconductor chip on the redistribution substrate and in the hole of the interconnect substrate, and a mold layer in a gap between the semiconductor chip and the interconnect substrate. The interconnect substrate includes a hole penetrating thereinside. The interconnect substrate includes base layers and a conductive member extending through the base layers. A top surface of the interconnect substrate is positioned either above or below the level of the top surface of the metal layer.

Abstract: An electronic device includes a substrate, a first electronic product arranged on the substrate, a second electronic product arranged on the substrate to be spaced apart from the first electronic product, and a heat dissipating assembly covering the first and second electronic products, the heat dissipating assembly comprising a heat dissipating chamber including a hermetically sealed space having a first portion having one or more gaps in which a flowable heat dissipation fluid is disposed and having a second portion in which a solid thermal conductive member is disposed to prevent the flow of the heat dissipation fluid across the second portion with respect to a plan view, wherein the first portion of the heat dissipating chamber has a first thermal conductivity and overlaps with the first electronic product in the plan view, wherein the solid thermal conductive member has a second thermal conductivity less than the first thermal conductivity, wherein the solid thermal conductive member overlaps with the se

Abstract: A physiological signal measurement apparatus includes a battery cover covering an area where a battery of a terminal device is detachably attached, a sensor unit detecting a physiological signal, the sensor unit being included in the battery cover, and a control unit controlling the sensor unit to detect the physiological signal, wherein the physiological signal measurement apparatus is detachably attached to the terminal device as the battery cover is detachably attached to the terminal device.

Abstract: A chip structure is provided. The chip structure includes: a first lower chip structure; and an upper chip structure on the first lower chip structure and having a pixel array region. The first lower chip structure includes: a first lower semiconductor substrate having a first side and a second side opposing each other; a first portion on the first side of the first lower semiconductor substrate; and a second portion on the second side of the first lower semiconductor substrate, the first portion of the first lower chip structure includes a gate wiring, the second portion of the first lower chip structure includes a second side wiring and a heating element, and the heating element is on the same plane as that of the second side wiring and has a length greater than that of the second side wiring.

Abstract: A surface temperature management method of mobile device is provided. The method includes sensing a temperature of an application processor in an operation mode of the mobile device; and controlling the application processor using the sensed temperature and a surface temperature management table to manage a surface temperature of a target part of the mobile device. The surface temperature management table includes information related to the temperature of the application processor corresponding to the surface temperature of the target part in the operation mode.