Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero.

Abstract: In a memory cell programming method, first through n-th programming operations are performed to program first through n-th bits of the n bits of data using the plurality of threshold voltage distributions. The first through n-th programming operations are performed sequentially. A threshold voltage difference between threshold voltage distributions used in the n-th programming operation is less than or equal to at least one threshold voltage difference between threshold voltage distributions used in the first through (n?1)-th programming operations.

Abstract: A semiconductor device includes a driving active region defined in a substrate and at least three driving transistors disposed at the driving active region. The driving transistors share one common source/drain, and each of the driving transistors includes individual source/drains being independent from each other. The common source/drain and the individual source/drains are disposed in the driving active region.

Abstract: A non-volatile memory device, including a substrate of a first conductivity type, the substrate including a plurality of wells of a second conductivity type, a plurality of memory cells in one of the plurality of wells of the second conductivity type, and a peripheral circuit including at least one first transistor of the second conductivity type on the substrate, and at least one second transistor of the first conductivity type in another one of the plurality of wells of the second conductivity type.

Abstract: Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device includes a plurality of stacked semiconductor layers and a plurality of memory cell transistors which is formed on each of a plurality of semiconductor layers and serially connected. Memory cell transistors disposed on different semiconductor layers are serially connected to include one cell string forming a current path in a plurality of semiconductor layers, a first selection transistor serially connected to one edge portion of the cell string and a second selection transistor serially connected to the other edge portion of the cell string.

Abstract: Provided are a selection transistor and a method of fabricating the same. A selection transistor can be formed on an active region in a semiconductor substrate to include a gate electrode that includes recessed portions of a sidewall of the gate electrode which are recessed inward adjacent lower portions of the gate electrode to define a T-shaped cross section of the gate electrode. A tunnel insulating layer can be located between the gate electrode and the active region.

Abstract: A flash memory device and/or methods of forming the flash memory device are provided, the flash memory device including a charge storage gate, a gate pattern over the charge storage gate, and a charge storage metal layer disposed between a side surface of the charge storage gate and the gate pattern. The methods include forming a preliminary charge storage gate pattern and forming a metal layer over a side surface of the preliminary charge storage gate pattern.

Abstract: A method of manufacturing a non-volatile memory device includes sequentially depositing a first insulation layer, a charge storage layer, and a second insulation layer on a substrate, forming a first opening through the resultant structure to expose the substrate, forming second and third openings through the second insulation layer to form a second insulation layer pattern, forming a conductive layer on the second insulation layer pattern, forming a photoresist pattern structure on the conductive layer, and forming simultaneously a common source line, at least one ground selection line, at least one string selection line, and a plurality of gate structures on the substrate by etching through the photoresist pattern structure, wherein the common source line and the gate structures are formed simultaneously on a substantially same level and of substantially same components.

Abstract: A replaceable ink reservoir adapted to an inkjet print system is provided. Since the inkjet print system of the conventional arts drives an air pump to inject air into the ink reservoir to discharge the ink stored in the ink storage pack to a printer cartridge, serious noise may be generated when the air pump is driven. In addition, in order to discharge the ink through the injection of the air, the ink reservoir should be one integrated body having a hermetically sealed structure, therefore, a user cannot visually check an ink storage level in the ink storage pack from the exterior of the ink reservoir. Further, since a nozzle connecting pipe is always connected to an ink outlet port connected to a front end of the ink storage pack, it is difficult to uniformly maintain discharge pressure of the ink, thereby causing an error image to be formed on a recording medium.

Abstract: Provided is a method of manufacturing a semiconductor device, by which a cell transistor formed on a cell array area of a semiconductor substrate employs a structure in which an electrode in the shape of spacers is used to form a gate and a multi-bit operation is possible using localized bits, and transistors having structures optimized to satisfy different requirements depending upon functions of the transistors can be formed on a peripheral circuit area which is the residual area of the semiconductor substrate. In this method, a cell transistor is formed on the cell array area.

Abstract: A non-volatile memory device includes a substrate, resistance patterns, a gate dielectric layer, a gate electrode pattern, a first impurity region and a second impurity region. The substrate has recesses. The recesses are filled with the resistance patterns. The resistance patterns include a material having a resistance that is variable in accordance with a voltage applied thereto. The gate dielectric layer is formed on the substrate. The gate electrode pattern is formed on the gate dielectric layer. The first and second impurity regions are formed in the substrate. The first impurity region and the second impurity region contact side surfaces of the resistance patterns. Further, the resistance patterns, the first impurity region and the second impurity region define a channel region. Thus, the non-volatile memory device may store data using a variable resistance of the resistance patterns so that the non-volatile memory device may have excellent operational characteristics.

Abstract: A NOR flash memory device includes a substrate having trenches that extend in a first direction and stepped portions that are arranged between the trenches. A bit region having a linear shape extends in a second direction substantially perpendicular to the first direction in the substrate. The bit region is doped with impurities. A first dielectric layer is on the substrate having the trenches. An electric charge trap layer is on the first dielectric layer. A second dielectric layer is on the electric charge trap layer. An upper electrode is on sidewalls of the trenches. The upper electrode has a spacer shape. Related fabrication methods are also described.

Abstract: In a non-volatile memory device allowing multi-bit and/or multi-level operations, and methods of operating and fabricating the same, the non-volatile memory device comprises, in one embodiment: a semiconductor substrate, doped with impurities of a first conductivity type, which has one or more fins defined by at least two separate trenches formed in the substrate, the fins extending along the substrate in a first direction; pairs of gate electrodes formed as spacers at sidewalls of the fins, wherein the gate electrodes are insulated from the semiconductor substrate including the fins and extend parallel to the fins; storage nodes between the gate electrodes and the fins, and insulated from the gate electrodes and the semiconductor substrate; source regions and drain regions, which are doped with impurities of a second conductivity type, and are separately formed at least at surface portions of the fins and extend across the first direction of the fins; and channel regions corresponding to the respective gate

Abstract: In a method of manufacturing a non-volatile memory device, a conductive structure is formed on a substrate. The conductive structure includes a tunnel oxide pattern, a first conductive pattern, a pad oxide pattern and a hard mask pattern. A trench is formed on the substrate using the conductive structure as an etching mask. An inner oxide layer is formed on an inner wall of the trench and sidewalls of the tunnel oxide pattern and the first conductive pattern. The inner oxide layer is cured, thereby forming a silicon nitride layer on the inner oxide layer. A device isolation pattern is formed in the trench, and the hard mask pattern and the pad oxide pattern are removed from the substrate. A dielectric layer and a second conductive pattern are formed on the substrate. Accordingly, the silicon nitride layer prevents hydrogen (H) atoms from leaking into the device isolation pattern.

Abstract: A dual display module having a first display panel and a second display panel, the dual display module including a bezel arranged between the first display panel and the second display panel, and having a penetration area between the first display panel and the second display panel; and a supporting member arranged between the bezel and the second display panel and supporting the second display panel, the supporting member having at least one protrusion unit that protrudes through the penetration area to face the first display panel.

Abstract: A frit sealing system and a method of manufacturing an organic light emitting display device by using the frit sealing system, and more particularly, a frit sealing system and a method of manufacturing an organic light emitting display device by using the frit sealing system, which includes a pressure member so as to physically pressurize a first substrate and a second substrate, thereby increasing adhesion of a frit when the first substrate and the second substrate are adhered to each other by using the frit.

Abstract: An hermetic sealing apparatus is discussed. The apparatus may include one or more of the following a glass mask disposed on an upper surface of a first substrate, a support member disposed on an upper surface of the glass mask, a laser irradiation member positioned spaced on the upper surface of the glass mask, a plurality of lower support members disposed in a contour region of a lower surface of the second substrate, and pressing members disposed on a lower surface of the lower support members.

Abstract: A frit sealing system for combining a first substrate and a second substrate using frit comprises a laser generating a laser beam, and a homogenizer normalizing the intensity of the laser beam within a cross section of the laser beam in the transverse direction. The frit sealing system further comprises a support apparatus configured to hold a first and a second substrate with frit interposed between them, wherein the frit is configured to be cured by heat generated from the laser beam and thereby solidifying and binding the first and the second substrates.