Abstract: In some embodiments, a semiconductor memory device includes a substrate that includes a cell array region and a peripheral circuit region. The semiconductor memory device further includes a device isolation pattern on the substrate. The device isolation pattern defines a first active region and a second active region within the cell array region and a third active region in the peripheral circuit region. The semiconductor memory device further includes a first common source region, a plurality of first source/drain regions, and a first drain region in the first active region. The semiconductor memory device further includes a second common source region, a plurality of second source/drain regions, and a second drain region in the second active region. The semiconductor memory device further includes a third source/drain region in the third active region. The semiconductor memory device further includes a common source line contacting the first and second common source regions.

Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: An anisotropic conductive film (ACF) is disclosed. The ACF includes a film, an adhesive layer positioned on the film, and one or more conductive balls within the adhesive layer. The conductive balls include a first core part having a first hardness, a second core part covering the first core part and having a second hardness that is greater than the first hardness, and a conductive part covering the second core part, respectively.

Abstract: According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover the exposed side surfaces of the lateral portions of the active structure. An effective channel length of a fin type transistor may be sufficiently ensured so that a short channel effect of the transistor may be prevented and the fin type transistor may have a high breakdown voltage.

Abstract: A nonvolatile memory device includes a semiconductor substrate of a first conductivity type, a plurality of word lines on the semiconductor substrate, each the plurality of word lines including a floating gate of a second conductivity type. A ground select line and a string select line are disposed on respective sides of word lines. An impurity region of the second conductivity type underlies a first word line adjacent the ground select line. The device may further include a second impurity region of the second conductivity type underlying a second word line adjacent the string select line. In still further embodiments, the device may further include third impurity regions of the second conductivity type underlying respective third word lines between the first word line and the second word line. Methods of forming such devices are also provided.

Abstract: A semiconductor device includes a first substrate, a plurality of cell transistors and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface. The plurality of cell transistors is formed extending on the first surface of the first substrate in a direction. The second substrate has an upper surface making contact with the second surface of the first substrate. Further, the upper surface of the second substrate has a bent structure to apply tensile stresses to the first substrate in the extending direction of the plurality of cell transistors. Thus, tensile stresses may be applied to the first substrate to improve the mobility of carriers in a channel region of the cell transistors.

Abstract: A deposition source which improves deposition characteristics and uniformity of a deposited film, and a method of manufacturing an organic light-emitting device. The deposition source includes a heat source, a heat transfer plate arranged on the heat source and adapted to receive heat generated by and transferred from the heat source and a planarization layer arranged on the heat transfer plate, the heat source to supply more heat per unit area to outer portions of the heat transfer plate that surrounds a central portion of the heat transfer plate than to the central portion of the heat transfer plate.

Abstract: In a method of manufacturing a non-volatile memory device, a conductive structure is formed on a substrate. The conductive structure includes a tunnel oxide pattern, a first conductive pattern, a pad oxide pattern and a hard mask pattern. A trench is formed on the substrate using the conductive structure as an etching mask. An inner oxide layer is formed on an inner wall of the trench and sidewalls of the tunnel oxide pattern and the first conductive pattern. The inner oxide layer is cured, thereby forming a silicon nitride layer on the inner oxide layer. A device isolation pattern is formed in the trench, and the hard mask pattern and the pad oxide pattern are removed from the substrate. A dielectric layer and a second conductive pattern are formed on the substrate. Accordingly, the silicon nitride layer prevents hydrogen (H) atoms from leaking into the device isolation pattern.

Abstract: A display device includes a wire substrate including a wire unit for driving the display device, an integrated circuit chip mounted at the wire substrate, and a pad unit extended from the wire unit to be disposed between the wire substrate and the integrated circuit chip. The pad unit is connected to the integrated circuit chip. The pad unit includes a first conductive layer extended from the wire unit, and a second conductive layer disposed on the first conductive layer. The hardness of the second conductive layer is less than the hardness of the first conductive layer.

Abstract: A method of programming data in a NAND flash memory device including at least one even bitline and at least one odd bitline, the method including programming N-bit data into first cells coupled to the at least one even bitline or the at least one odd bitline and programming M-bit data into second cells coupled to the other of the at least one even bitline and the at least one odd bitline, where N is a natural number greater than one and M is a natural number greater than N.

Abstract: A resin fluid dispensing apparatus includes a container arranged to receive a resin fluid, a first connection unit connected to the container, a pressure chamber arranged configured to contain the resin fluid transported from the first volume through the first connection unit from the first volume received into a second volume in a pressure chamber. A pressure unit comprising a pressure plate directly pressurizing the resin fluid in the second volume. A dispenser arranged to receive the pressurized resin fluid transported from the second volume through a second connection unit connected to the pressure chamber. The dispenser dispensing the received pressurized resin fluid through a syringe.

Abstract: A thin film deposition apparatus for use with a substrate having deposition regions separated by non-deposition regions includes a deposition source, a first nozzle assembly disposed in front of the deposition source, at least one barrier wall assembly disposed in front of the first nozzle assembly, and a second nozzle assembly disposed between the barrier wall assembly and the substrate. At least one deposition blade is disposed between the deposition source and the first nozzle assembly, the first nozzle assembly and the barrier wall assembly, the barrier wall assembly and the second nozzle assembly, or the second nozzle assembly and the substrate. Using the deposition blade, the deposition of the deposition material on the non-deposition regions of the substrate may be minimized during a deposition process.

Abstract: A thin film deposition apparatus includes a deposition source that is disposed opposite to a substrate and holds a deposition material that is vaporized; a first nozzle unit disposed between the substrate and the deposition source and having first slit units arranged in a first direction of the substrate; a second nozzle unit disposed between the first nozzle unit and the substrate and having second slit units arranged in the first direction of the substrate; and at least one barrier member assembly disposed between the first nozzle unit and the second nozzle unit and partitioning the space between the first nozzle unit and the second nozzle unit. A deposition blade is optionally disposed in any space formed between the first nozzle unit and the second nozzle unit during a stand-by mode to prevent the deposition of the deposition material from being deposited onto undesirable regions of the chamber.

Abstract: Integrated circuit nonvolatile memory devices are manufactured by forming a variable resistance layer on an integrated circuit substrate. The variable resistance layer includes grains that define grain boundaries between the grains. Conductive filaments are formed along at least some of the grain boundaries. Electrodes are formed on the variable resistance layer. The conductive filaments may be formed by implanting conductive ions into at least some of the grain boundaries. Moreover, the variable resistance layer may be a variable resistance oxide of a metal, and the conductive filaments may be the metal. Related devices are also disclosed.

Abstract: A semiconductor device may include a fin structure having source/drain regions and channel fins connected between source/drain patterns. A gate insulation layer may be provided on the channel fins. A gate electrode may include lower gate patterns and an upper gate pattern. The lower gate patterns may extend in a vertical direction and contact the gate insulation layer. The upper gate pattern may extend in a second horizontal direction substantially perpendicular to the first horizontal direction. The upper gate pattern may be connected to upper portions of the lower gate patterns.

Abstract: In one embodiment, a semiconductor memory device includes a substrate having first and second active regions. The first active region includes a first source and drain regions and the second active region includes a second source and drain regions. A first interlayer dielectric is located over the substrate. A first conductive structure extends through the first interlayer dielectric. A first bit line is on the first interlayer dielectric. A second interlayer dielectric is on the first interlayer dielectric. A contact hole extends through the second and first interlayer dielectrics. The device includes a second conductive structure within the contact hole and extending through the first and second interlayer dielectrics. A second bit line is on the second interlayer dielectric. A width of the contact hole at a bottom of the second interlayer dielectric is less than or substantially equal to a width at a top of the second interlayer dielectric.

Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

Abstract: A semiconductor device includes a first substrate, a plurality of cell transistors and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface. The plurality of cell transistors is formed extending on the first surface of the first substrate in a direction. The second substrate has an upper surface making contact with the second surface of the first substrate. Further, the upper surface of the second substrate has a bent structure to apply tensile stresses to the first substrate in the extending direction of the plurality of cell transistors. Thus, tensile stresses may be applied to the first substrate to improve the mobility of carriers in a channel region of the cell transistors.

Abstract: Example embodiments relate to methods of fabricating a non-volatile memory device. According to example embodiments, a method of fabricating a non-volatile memory device may include forming at least one gate structure on an upper face of a substrate. The at least one gate structure may include a tunnel insulation layer pattern, a charge storing layer pattern, a dielectric layer pattern and a control gate. According to example embodiments, a method of fabricating a non-volatile memory device may also include forming a silicon nitride layer on the upper face of the substrate to cover the at least one gate structure, forming an insulating interlayer on the silicon nitride layer on the upper face of the substrate, and providing an annealing gas toward the upper face of the substrate and a lower face of the substrate to cure defects of the tunnel insulation layer pattern.