Abstract: A CMOS image sensor includes PDAF pixels distributed in an array of image pixels in plan view. Each PDAF pixel includes m×m binned photodiodes, a PDAF color filter overlying the binned photodiodes and laterally surrounded by a first isolation structure, and a PDAF micro-lens overlying the PDAF color filter. A first horizontal distance between a center of the PDAF color filter and a center of the binned photodiodes varies depending on a location of the PDAF pixel in plan view in the CMOS image sensor. Additionally, the first isolation structure includes a first low-n dielectric grid, a second low-n dielectric grid underlying the first low-n dielectric grid, and a metal grid enclosed by the second low-n dielectric grid. The second low-n dielectric grid includes a filler dielectric material different from a second low-n dielectric grid material. Thus, quantum efficiency and uniformity of the CMOS image sensor are improved.

Abstract: An electrical connector assembly includes: a male connector, provided with a conductive shell; a first substrate, accommodated in the conductive shell and used to transmit receiving signals; a second substrate, accommodated in the conductive shell and used to transmit sending signals; a shielding sheet, located between the first substrate and the second substrate; a female connector, provided with a first conductive body and a second conductive body; a plurality of first signal terminals, accommodated in the first conductive body and used to transmit receiving signals; and a plurality of second signal terminals, accommodated in the second conductive body and used to transmit sending signals. The first signal terminals and the first substrate are electrically contacted to each other. The second signal terminals and the second substrate are electrically contacted to each other. The first conductive body and/or the second conductive body are used to lap joint with the shielding sheet.

Abstract: A semiconductor device includes a substrate having a first region and a second region separated from the first region by distance to define a space therebetween. A first semiconductor device including a gate dielectric is on the first region. The first semiconductor device can implement a FinFet-based input/output (I/O) device in the first region. A second semiconductor device excluding a gate dielectric is on the second region. The second semiconductor device can implement a nanosheet-based logic device in the second region.

Abstract: During operation, a computer system may provide instructions to access points in an indoor environment to measure relative distances between the access points. Then, the computer system may receive the measured relative distances. Moreover, the computer system may calculate geographic locations of the access points based at least in part on the measured relative distances. Next, the computer system may select potential anchor access points in the access points, and may provide, to an electronic device, information specifying the potential anchor access points. Furthermore, the computer system may receive, from the electronic device, second information specifying anchor access points in the potential access points and defined locations of the anchor access points. Additionally, the computer system may update the geographic locations based at least in part on the defined of the anchor access points, and may provide, to the access points, the updated geographic locations.

Abstract: A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.

Abstract: An image capturing unit includes an imaging element and a dual-shot injection-molded optical folding element that are adjacent to each other. The imaging element is configured for an imaging light to pass through. The dual-shot injection-molded optical folding element includes a first part and a second part. The first part is made of transparent material. The first part has a reflective surface configured to reflect the imaging light. The second part is made of opaque material, and the second part is fixed at periphery of the first part. The second part includes a supporting portion configured to support the dual-shot injection-molded optical folding element. The supporting portion maintains the dual-shot injection-molded optical folding element at a predetermined position corresponding to the imaging element through mechanism assembly.

Abstract: A method includes following steps. A first precursor is pulsed over a substrate such that first precursor adsorbs on a first region and a second region of the substrate. A first plurality of the first precursor adsorbing on the first region is then removed using a plasma, while leaving a second plurality of the first precursor adsorbing on the second region. A second precursor is then pulsed to the substrate to form a monolayer of a film on the second region and a material on the first region. The material is then removed using a plasma. The substrate is biased during removing the material.

Abstract: A semiconductor device includes a nucleation layer, a buffer layer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. The nucleation layer includes a composition that includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer is disposed on and forms an interface with the nucleation layer. The buffer layer has a concentration of the first element oscillating within the buffer layer, such that the concentration of the first element varies as an oscillating function of a distance within a thickness of the buffer layer. Spacings among adjacent peaks of the oscillating function change from wide to narrow with respect to a first reference point within the buffer layer. The first and second nitride-based semiconductor layer, S/D electrodes, and a gate electrode are disposed on the buffer layer.

Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

Abstract: The present disclosure provides systems and methods for sorting a cell. The system may comprise a flow channel configured to transport a cell through the channel. The system may comprise an imaging device configured to capture an image of the cell from a plurality of different angles as the cell is transported through the flow channel. The system may comprise a processor configured to analyze the image using a deep learning algorithm to enable sorting of the cell.

Abstract: The present disclosure relates to systems and methods for real and virtual object interactions in augmented reality environments are disclosed. The system comprises areal object detection module to receive multiple image pixels and the corresponding depths of at least one initiative object, a real object recognition module to determine a shape, a position, and a movement of the initiative object; a virtual object display module to display a virtual target object, a collision module to determine whether the at least one initiative object collides into a virtual target object and, an interaction module for determining an action responding to an event based on at least one of an object recognition determination from the real object recognition module, a collision determination from the collision module, and a type of the virtual target object.

Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

Abstract: A variable aperture module includes a blade assembly, a positioning element, a driving part and pressing structures. The blade assembly includes movable blades disposed around an optical axis to form a light passable hole with an adjustable size. Each movable blade has a positioning hole and a movement hole adjacent thereto. The positioning element includes positioning structures disposed respectively corresponding to the positioning holes. The driving part includes a rotation element disposed corresponding to the movement holes and is rotatable with respect to the positioning element. The pressing structures are disposed respectively corresponding to the movable blades. Each pressing structure is at least disposed into at least one of the positioning hole and the movement hole of the corresponding movable blade. Each pressing structure at least presses against at least one of the corresponding one positioning structure and the rotation element.

Abstract: An electronic device includes a substrate, a first silicon transistor, a second silicon transistor and a first oxide semiconductor transistor. The first silicon transistor, the second silicon transistor and the first oxide semiconductor transistor are disposed on the substrate. The first silicon transistor has a first terminal electrically connected to a first voltage level, a second terminal and a control terminal. The second silicon transistor has a first terminal electrically connected to the second terminal of the first silicon transistor, a second terminal electrically connected to a second voltage level, and a control terminal electrically connected to the control terminal of the first silicon transistor. The first oxide semiconductor transistor has a first terminal electrically connected to the first terminal of the second silicon transistor. Wherein, a voltage value of the first voltage level is greater than a voltage value of the second voltage level.

Abstract: Among other things, the present invention is related to bio/chemical sampling, sensing, assays and applications.

Abstract: An electronic device may include scaling circuitry to scale input pixel data to a greater resolution. The directional scaling circuitry may include first interpolation circuitry to receive best mode data, including one or more angles corresponding to content of the image and interpolate first pixel values at first pixel positions diagonally offset from input pixel positions of the input pixel data based on the best mode data and input pixel values corresponding to the input pixel positions. The directional scaling circuitry may also include second interpolation circuitry to receive the best mode data and the input pixel values and interpolate second pixel values at second pixel positions horizontally or vertically offset from the input pixel positions based at least in part on the best mode data and the input pixel values.

Abstract: Systems and methods are provided for wireless power transfer in a vehicle. A wireless power transfer system can include a high-frequency alternating current (HFAC) inverter electrically coupled to the power source and a transmitter to wirelessly transmit a HFAC power signal to at least one device of a vehicle, such as sensors (e.g., LiDAR, GPS etc.) and cameras. The HFAC power signal provides wireless power and a data signal to the at least one device of a vehicle. The wireless power transfer system can eliminate the need for cabling and wires to provide power to the device. Wireless power transfer can include use or a data modulation circuit and a pulse current source to inject a pulse current to the HFAC power signal as superimposed data. System configurations can power a plurality of devices. Systems can includes a plurality of HFAC inverters and transmitters to power multiple sets of devices.

Abstract: An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive pad having a generally planar top surface that includes a cavity having a bottom surface and sidewalls extending from the bottom surface of the cavity to the top surface of the pad. An electronic device is attached to the top surface of the electrically conductive pad. A wire bond is attached from the electronic device to the bottom surface of the cavity. A molding compound encapsulates the electronic device.

Abstract: A method for wireless communication performed by a user equipment (UE) is provided. The UE includes a plurality of antenna panels. The method includes transmitting, to a Base Station (BS), a UE capability message that includes a number of the plurality of antenna panels; and transmitting, to the BS, a panel report that includes information of the plurality of antenna panels, the information associated with at least one of a Synchronization Signal Block (SSB) and a Channel State Information Reference Signal (CSI-RS).

Abstract: A homogeneous assay method that employs a device is provided. In some embodiments, the device contains a pair of plates that can be opened and closed. The sample is placed between two plates. In some embodiments, the thickness of the sample in a closed configuration, the concentration of labels, and amplification factor of the amplification surface are configured to make the label(s) bound on the amplification surface visible without washing away of the unbound labels.