Patents by Inventor Chou

Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11935894
    Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu
  • Publication number: 20240088182
    Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Chien Yu, Ting-Cheng Chang, Wen-Hau Wu, Chih-Kung Chang
  • Publication number: 20240088703
    Abstract: High voltage discharge is provided. A system can include an electric motor of an electric vehicle electrically connected to a capacitor. A switching component can be connected with and intermediary to the electric motor and the capacitor. A controller can cause the switching component to enter a first state to cause the electric motor to convert electrical power of the capacitor to mechanical power to propel the electric vehicle, or convert mechanical power from a drive system of the electric vehicle to electrical power to charge the capacitor. The controller can cause the switching component to enter, in response to detection by the controller of an indication to discharge the capacitor, a second state to isolate the electric motor from the capacitor.
    Type: Application
    Filed: September 12, 2022
    Publication date: March 14, 2024
    Inventors: Boru Wang, Chia-Chou Yeh, Charles John Scanlon
  • Publication number: 20240083147
    Abstract: Provided is a laminated glass in which creasing is reduced in the interlayer film and having excellent appearance although an interlayer film including a film having optical properties is used.
    Type: Application
    Filed: December 21, 2021
    Publication date: March 14, 2024
    Applicant: SEKISUI CHEMICAL CO., LTD.
    Inventors: Kinryou CHOU, Atsushi NOHARA
  • Publication number: 20240087961
    Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Ju CHOU, Chih-Chung Chang, Jun-Ming Kuo, Che-Yuan Hsu, Pei-Ling Kao, Chen-Hsuan Liao
  • Publication number: 20240085671
    Abstract: An annular light trapping component includes an inner surface, an outer surface, an object-side surface and an image-side surface. The inner surface includes multiple L-shaped annular grooves. The annular light trapping component includes multiple stripe-shaped structures in the L-shaped annular grooves. The L-shaped annular grooves include an object-side L-shaped annular groove closest to the object-side surface and an image-side L-shaped annular groove closest to the image-side surface. A bottom diameter of the image-side L-shaped annular groove is larger than a bottom diameter of the object-side L-shaped annular groove. Each L-shaped annular groove includes a first side and a second side located between the object-side surface and the image-side surface. The stripe-shaped structures are disposed on the first side or the second side. A degree of inclination between the first side and the central axis is larger than a degree of inclination between the second side and the central axis.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Ming-Ta CHOU, Cheng-Feng LIN, Wei-Hung WENG
  • Publication number: 20240087128
    Abstract: This application describes systems and methods for detecting depth in deep trench isolation with semiconductor devices using test key transistors. An method comprises: capturing, by an image sensor, an image; generating a plurality of chrominance channels by converting the image into luminance-chrominance space; performing homogeneous region segmentation on the plurality of chrominance channels to generate one or more regions of interest in the plurality of chrominance channels; and projecting the regions of interest onto eigen-illuminant images to determine gray color pixels on the image, wherein the eigen-illuminant images are generated via performing a machine learning algorithm on a training set of images captured by the image sensor.
    Type: Application
    Filed: September 8, 2022
    Publication date: March 14, 2024
    Inventors: Yang-Ting CHOU, Zhaojian LI
  • Publication number: 20240084871
    Abstract: A device for controlling fluid flow in a shock assembly is disclosed. The device includes a single adjustable fluid circuit configured for controlling a damping force associated with multiple compression forces. The single adjustable fluid circuit comprises a fluid passageway through a base valve and a positionally adjustable piston assembly with a floating shim stack positioned at one end of the fluid passageway, the positionally adjustable piston assembly with the floating shim stack configured for selectively blocking a flow of fluid through the fluid passageway.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 14, 2024
    Applicant: Fox Factory, Inc.
    Inventor: Yi-Hong Chou
  • Publication number: 20240089184
    Abstract: Some embodiments provide a method for evaluating a network. The method identifies multiple network correctness requirements configured for the network. The method instantiates a separate respective evaluation program instance for each respective identified network correctness requirement to evaluate the respective network correctness requirement. At least two evaluation program instances are instantiated on different machines. Each respective evaluation program instance stores in a respective memory a respective set of network device data to evaluate the respective network correctness requirement. Each set of network device data requires less memory than storing network device data for the entire network.
    Type: Application
    Filed: September 15, 2022
    Publication date: March 14, 2024
    Inventors: Santhosh Prabhu Muraleedhara Prabhu, Kuan-Yen Chou, Aanand Nayyar, Giri Prashanth Subramanian, Wenxuan Zhou, Philip Brighten Godfrey
  • Publication number: 20240089608
    Abstract: The present invention relates to a dynamic image generating method and a dynamic image sensor thereof. The dynamic image sensor includes a first exposure pixel, a second exposure pixel and an image processing module. The dynamic image sensor applies the dynamic image generating method, which generates the default short-exposure image signal by exposing the first exposure pixel for default short-exposure time, and exposing the second exposure pixel for default long-exposure time to generate the default long-exposure image signal. The image processing module confirms whether the default short-exposure image and the default long-exposure image signals are between the lower and upper limits of pinching.
    Type: Application
    Filed: August 25, 2023
    Publication date: March 14, 2024
    Inventors: Ping-Hung Yin, Yung-Ming Chou
  • Publication number: 20240089257
    Abstract: Some embodiments provide a method for evaluating a network correctness requirement at an evaluation program instance assigned to evaluate a particular network correctness requirement. The method identifies data message properties associated with the particular network correctness requirement. The method evaluates the particular network correctness requirement by (i) determining a path through a set of network devices for a data message having the identified data message properties and (ii) from a data storage that stores data message processing rules for a plurality of network devices including the set of network devices and additional network devices, retrieving and storing in memory data specifying data message processing rules for the set of network devices to use in evaluating the particular network correctness requirement.
    Type: Application
    Filed: September 15, 2022
    Publication date: March 14, 2024
    Inventors: Santhosh Prabhu Muraleedhara Prabhu, Kuan-Yen Chou, Aanand Nayyar, Giri Prashanth Subramanian, Wenxuan Zhou, Philip Brighten Godfrey
  • Publication number: 20240090201
    Abstract: A semiconductor device includes a plurality of drain regions in a substrate; a plurality of capacitor plugs on the plurality of drain regions; a plurality of lower electrodes on the plurality of capacitor plugs and respectively including a U-shaped cross-sectional profile; a lower supporting layer above the substrate, against on outer surfaces of the plurality of lower electrodes, and including: a plurality of first openings along the lower supporting layer and between the plurality of lower electrodes; and a higher supporting layer above the lower supporting layer, against on the outer surfaces of the plurality of lower electrodes, and including: a plurality of second openings along the higher supporting layer and topographically aligned with the plurality of first openings. The widths of the plurality of first openings and the widths of the plurality of second openings are substantially the same.
    Type: Application
    Filed: September 18, 2023
    Publication date: March 14, 2024
    Inventor: LIANG-PIN CHOU
  • Publication number: 20240090019
    Abstract: A method for LBT failure detection performed by a UE is provided. The method includes: receiving, by a MAC entity of the UE, an LBT failure indication from a lower layer for all UL transmissions; increasing an LBT failure counter when the MAC entity receives the LBT failure indication; determining an LBT failure event occurs when the LBT failure counter is greater than or equal to a threshold; and resetting the LBT failure counter after the MAC entity has not received the LBT failure indication for a time period.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 14, 2024
    Inventors: Hung-Chen Chen, Chie-Ming Chou, Chia-Hung Wei, Mei-Ju Shih
  • Publication number: 20240084445
    Abstract: A leak check is performed on a semiconductor wafer processing tool that includes a process chamber and process gas lines, and a semiconductor wafer is processed using the semiconductor wafer processing tool if the leak check passes. Each gas line includes a mass flow controller (MFC) and normally closed valves including an upstream and downstream valves upstream and downstream of the MFC. Leak checking includes: leak checking up to the downstream valves of the gas lines with the upstream valves closed and the downstream valves of the gas lines closed; and leak checking up to the upstream valve of each the process gas line with the upstream valves of the of the process gas lines closed and with the downstream valve of the of the process gas line being leak checked open and the downstream valve of every other process gas line closed.
    Type: Application
    Filed: January 4, 2023
    Publication date: March 14, 2024
    Inventors: Chih-Wei Chou, Yuan-Hsin Chi, Chih-Hao Yang, Hung-Chih Wang, Yu-Chi Liu, Sheng-Yuan Lin
  • Publication number: 20240086221
    Abstract: Some embodiments provide a method for an orchestration program instance assigned a particular network device in a network. Each network device of multiple network devices is assigned to a different orchestration program instance in a cluster. The method receives a notification message that a configuration for the particular network device has been modified. In response to the notification message, the method identifies a set of network correctness requirements to be evaluated for the network. The method sends a separate notification message for each identified network correctness requirement specifying that the particular network device configuration has been modified so that a set of evaluation program instances can re-evaluate any network correctness requirements dependent on the particular network device.
    Type: Application
    Filed: September 15, 2022
    Publication date: March 14, 2024
    Inventors: Santhosh Prabhu Muraleedhara Prabhu, Kuan-Yen Chou, Aanand Nayyar, Giri Prashanth Subramanian, Wenxuan Zhou, Philip Brighten Godfrey
  • Publication number: 20240088154
    Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed directly on an upper surface of the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Alexander Kalnitsky, Kong-Beng Thei, Ming Chyi Liu, Shih-Chung Hsiao, Jhih-Bin Chen
  • Publication number: 20240088127
    Abstract: In an integrated circuit, the gates of a first high-threshold transistor and a first low-threshold transistor are connected together, and the gates of a second high-threshold transistor and a second low-threshold transistor are connected together. The drain of the first high-threshold transistor is conductively connected to the source of the first low-threshold transistor, and the drain of the second high-threshold transistor is conductively connected to the source of the second low-threshold transistor. The gates of the first low-threshold transistor and the second low-threshold transistor are conductively connected to the drain of the first low-threshold transistor. The threshold-voltage of the first high-threshold transistor is larger than a threshold-voltage of the first low-threshold transistor. The threshold-voltage of the second high-threshold transistor is larger than a threshold-voltage of the second low-threshold transistor.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Yu-Tao YANG, Wen-Shen CHOU, Yung-Chow PENG
  • Publication number: 20240089611
    Abstract: The present invention relates to a method of image fusion, which uses the brightness difference of the current frame and the previous frame to determine whether the pixel in a frame image is static or dynamic. If the current pixel is static, the previous corresponding pixel is superimposed onto the current pixel; if the current pixel is dynamic, the previous corresponding pixel is replaced with the current pixel.
    Type: Application
    Filed: September 7, 2023
    Publication date: March 14, 2024
    Inventors: Ping-Hung Yin, Yung-Ming Chou, Bo-Jia Lin, Yu-Sheng Liao
  • Publication number: 20240085676
    Abstract: A light-folding element includes an object-side surface, an image-side surface, a reflection surface and a connection surface. The reflection surface is configured to reflect imaging light passing through the object-side surface to the image-side surface. The connection surface is connected to the object-side, image-side and reflection surfaces. The light-folding element has a recessed structure located at the connection surface. The recessed structure is recessed from the connection surface an includes a top end portion, a bottom end portion and a tapered portion located between the top end and bottom end portions. The top end portion is located at an edge of the connection surface. The tapered portion has two tapered edges located on the connection surface. The tapered edges are connected to the top end and bottom end portions. A width of the tapered portion decreases in a direction from the top end portion towards the bottom end portion.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Min-Chun LIAO, Lin An CHANG, Ming-Ta CHOU, Jyun-Jia CHENG, Cheng-Feng LIN, Ming-Shun CHANG
  • Publication number: 20240086087
    Abstract: Systems, methods, circuits, and apparatuses for managing integrated circuits in memory devices are provided. In one aspect, a system includes a semiconductor device configured to store data, and a controller communicatively coupled to the semiconductor device. The controller is configured to send, to the semiconductor device, an instruction requesting transmission of the data; in response to determining that a predetermined time duration has elapsed after sending the instruction, initiate transmission of a read enable signal to the semiconductor device; receive, from the semiconductor device, a data strobe signal; and, in response to determining that the data strobe signal has a frequency matching a frequency of the read enable signal, read the data from the semiconductor device.
    Type: Application
    Filed: September 8, 2022
    Publication date: March 14, 2024
    Applicant: Macronix International Co., Ltd.
    Inventors: Shun-Li Cheng, Shih-Chou Juan