Patents by Inventor Chou

Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240053790
    Abstract: A monitor includes a casing assembly, a light-emitting module and a display panel. The casing assembly includes a casing and a support frame. The support frame is disposed in the casing. The support frame includes an accommodation portion and at least one support portion, the accommodation portion is connected to the casing, the support portion is connected to the accommodation portion and protrudes from the accommodation portion. The light-emitting module is disposed in the accommodation portion. The display panel is supported by the at least one support portion.
    Type: Application
    Filed: December 21, 2022
    Publication date: February 15, 2024
    Inventors: CHUNLEI ZHAO, Liang Yang, YAO-CHEN YANG, chia-jang Chen, chih chou Chou
  • Publication number: 20240057153
    Abstract: A user device (UE) for scheduling an uplink transmission assignment with a base station that communicates with the user device via a shared carrier, receives, from the base station, a configuration that indicates (i) a first channel access procedure for the user device to perform prior to transmitting an uplink transmission and (ii) at least one occasion at which the user device is to transmit the uplink transmission (1602); receives, from the base station via the shared carrier, a signal indicating at least a portion of a transmission time period during which the shared carrier is available to the base station (1604); and performs the first channel access procedure or a second channel access procedure before transmitting the uplink transmission based at least in part on whether the occasion is within the transmission time period (1606).
    Type: Application
    Filed: October 6, 2020
    Publication date: February 15, 2024
    Inventors: Kao-Peng Chou, Chih-Hsiang Wu
  • Publication number: 20240055525
    Abstract: A method of forming a semiconductor device includes forming a dummy gate structure across a fin protruding from a substrate, forming gate spacers on opposite sidewalls of the dummy gate structure, forming source/drain epitaxial structures on opposite sides of the dummy gate structure, forming a first interlayer dielectric (ILD) layer on the source/drain epitaxial structures and outer sidewalls of the gate spacers, replacing the dummy gate structure with a replacement gate structure, etching back the replacement gate structure to form a first recess between the gate spacers, forming a source/drain contact in the first ILD layer, and forming a second interlayer dielectric (ILD) layer to fill in the first recess between the gate spacers and over the source/drain contact.
    Type: Application
    Filed: August 11, 2022
    Publication date: February 15, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien HUANG, Tze-Liang LEE, Jr-Hung LI, Chi-Hao CHANG, Hao-Yu CHANG, Pei-Yu CHOU
  • Publication number: 20240050987
    Abstract: A semiconductor device and a method are provided. The semiconductor device includes a first semiconductor component, a bonding layer and a second semiconductor component. The first semiconductor component includes a first transistor formed on a substrate and a second transistor formed on the substrate and separated from the first transistor. The bonding layer is provided on the first semiconductor component. The second semiconductor component is provided on the bonding layer and includes an acoustic transducer. The acoustic transducer is controlled by the first transistor and the second transistor to execute a photoacoustic sensing. The acoustic transducer comprises a space gap and a least a portion of the space gap is surrounded by the bonding layer.
    Type: Application
    Filed: August 11, 2022
    Publication date: February 15, 2024
    Inventors: MING-HSIEN YANG, CHUN-HAO CHOU, KUO-CHENG LEE, SHENG KAI YEH
  • Publication number: 20240053875
    Abstract: System, methods, and other embodiments described herein relate to controlling display attributes within a visual interface for enhancing stimuli and responses of a user. In one embodiment, a method includes selecting display attributes related to a first layer of an image and a second layer of the image, and the first layer includes a symbol, the second layer represents a background of the symbol, and the image is associated with an interface to control a component. The method also includes oscillating, at first multiple of a frequency, between first values of the display attributes representing colors that are different for displaying the first layer, and the colors changing by a duty cycle associated with the first multiple of the frequency. The method also includes oscillating, at a second multiple of the frequency, between second values for displaying the second layer in parallel with the first layer until detecting a selection associated with the interface.
    Type: Application
    Filed: October 24, 2023
    Publication date: February 15, 2024
    Inventors: Chungchih Chou, Muhamed Kusay Farooq, Ercan Mehmet Dede
  • Publication number: 20240050518
    Abstract: This disclosure relates to antigenic EBV polypeptides and their use in eliciting antibodies against EBV. Also disclosed are antigenic polypeptides comprising an EBV polypeptide and a ferritin protein.
    Type: Application
    Filed: June 15, 2023
    Publication date: February 15, 2024
    Applicant: SANOFI
    Inventors: Gary J. Nabel, Chih-Jen Wei, Laura Nguyen, Kurt Swanson, Te-Hui Chou, Stefan Koester
  • Publication number: 20240055476
    Abstract: A method of fabricating a semiconductor device includes providing a dummy structure that includes channel layers, inner spacers disposed between adjacent ones of the channel layers, and a gate structure extending lengthwise in a first direction. A first trench extending lengthwise perpendicular to the first direction is formed, which divides the gate structure into segments. A first isolation feature is deposited in the first trench. The method also includes etching the gate structure and the channel layers to form a second trench extending lengthwise in the first direction. The second trench exposes the inner spacers. A second isolation feature is deposited in the second trench. The second isolation feature intersects the first isolation feature in a top view of the semiconductor device.
    Type: Application
    Filed: April 10, 2023
    Publication date: February 15, 2024
    Inventors: Cheng-Wei Chang, Shahaji B. More, Lun-Kuang Tan, Chi-Yu Chou, Yueh-Ching Pai
  • Publication number: 20240055452
    Abstract: A semiconductor image sensing structure includes a substrate, an isolation structure, an anti-reflection structure, at least one optical element and a transistor. The substrate has at least one photodiode region. The isolation structure is disposed in the substrate and surrounds the photodiode region. The anti-reflection structure covers the photodiode region. The optical element is disposed over the anti-reflection structure and corresponds to the photodiode region. The transistor is disposed under the photodiode region.
    Type: Application
    Filed: August 9, 2022
    Publication date: February 15, 2024
    Inventors: MING-HSIEN YANG, CHUN-LIANG LU, CHUN-HAO CHOU, KUO-CHENG LEE
  • Publication number: 20240055274
    Abstract: A semiconductor package carrier board structure includes a plurality of carrier board bodies and a plurality of supporting bumps. The carrier board body includes a build-up circuit structure and a plurality of conductive blocks bonded to the build-up circuit structure. Adjacent ones of the carrier board bodies are connected to each other with their corresponding conductive blocks. An area formed by the adjacent conductive blocks defines a cutting path. An opening is formed on a surface of each of the conductive blocks at the cutting path. The supporting bumps are erected between the adjacent openings. As such, each of the supporting bumps corresponds to a position overlapping the cutting path to provide the support function of the semiconductor package carrier board structure when performing the semiconductor packaging operation. After performing the singulation operation, the supporting bumps can be completely removed and one side of the openings can be exposed.
    Type: Application
    Filed: August 15, 2023
    Publication date: February 15, 2024
    Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Pao-Hung CHOU, Ming-Yeh CHANG
  • Publication number: 20240050009
    Abstract: A cardiac information dynamic display system comprises: one or more electrodes configured to record sets of electric potential data representing cardiac activity at a plurality of time intervals; and a cardiac information console, comprising: a signal processor configured to: calculate sets of cardiac activity data at the plurality of time intervals using the recorded sets of electric potential data, wherein the cardiac activity data is associated with surface locations of one or more cardiac chambers; and a user interface module configured to display a series of images, each image comprising: a graphical representation of the cardiac activity. Methods of providing cardiac activity data are also provided.
    Type: Application
    Filed: July 6, 2022
    Publication date: February 15, 2024
    Inventors: Daniel WELSH, Derrick Ren-yu Chou, Haizhe ZHANG, Leo MARIAPPAN, Min ZHU, Steven Anthony YON, Xinwei SHI, Graydon Ernest BEATTY, Nathan ANGEL, Weiyi TANG, Christoph SCHARF, Christopher J. FLAHERTY, Ahmad Falahatpisheh
  • Publication number: 20240056055
    Abstract: A glitch-free low-pass filter circuit includes an integrating circuit, a Schmitt trigger, a first feedback logic circuit and a second feedback logic circuit. The integrating circuit is used to integrate an input signal to generate an integral signal. The Schmitt trigger is used to receive the integral signal to generate a hysteresis signal. The first feedback logic circuit is used to pull the integral signal to a reset voltage or up to the set voltage based on an inverted input signal and an inverted hysteresis signal, wherein the inverted input signal and the inverted hysteresis signal are generated by performing an inversion process. The second feedback logic circuit is used to pull the integral signal down to the reset voltage or up to the set voltage based on the inverted hysteresis signal and an output signal, wherein the output signal is generated by performing the inversion process twice.
    Type: Application
    Filed: April 11, 2023
    Publication date: February 15, 2024
    Inventor: CHOU-CHUAN CHEN
  • Publication number: 20240053539
    Abstract: The present disclosure provides a calibration system for wavelength-division multiplexing (WDM), a WDM system, and a calibrating method for WDM. The calibration system includes heating devices, an optical sensor, and an electrical device. When the optical sensor receives no beam with energy exceeding a threshold value from a first channel, the optical sensor transmits a first signal to the electrical device. In response to the first signal, the electrical device is configured to control the one or more of the heating devices to heat one or more of channels. When the optical sensor receives a beam having energy exceeding the threshold value from the first channel, the optical sensor transmits a second signal to the electrical device. In response to the second signal, the electrical device is configured to control the one or more of the heating devices to maintain the temperature of the one or more of the channels.
    Type: Application
    Filed: October 22, 2023
    Publication date: February 15, 2024
    Inventors: TAI-CHUN HUANG, LAN-CHOU CHO, CHEWN-PU JOU, STEFAN RUSU
  • Patent number: 11899273
    Abstract: An imaging lens module with auto focus function includes an imaging lens assembly, an electromagnetic driving component assembly and a lens carrier. The imaging lens assembly has an optical axis. The electromagnetic driving component assembly drives the imaging lens assembly to move in a direction parallel to the optical axis by a Lorentz force. The imaging lens assembly is mounted to the lens carrier such that the imaging lens assembly can be wholly driven by the Lorentz force. The lens carrier includes an object-side part, a mounting structure and a plurality of plate portions. The object-side part includes a tip-end minimal aperture configured for light to travel through; and a tapered surface which surrounds an area tapered off from image side to object side. The mounting structure and the plate portions are configured for at least a part of the electromagnetic driving component assembly to be mounted thereto.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: February 13, 2024
    Assignee: LARGAN DIGITAL CO., LTD.
    Inventors: Chun-Hua Tsai, Ming-Ta Chou, Ming-Shun Chang
  • Patent number: 11898916
    Abstract: A semiconductor device includes a plurality of active area structures. One or more active devices include portions of the plurality of active area structures. A metal layer is formed on the plurality of active area structures and separated from the one or more active devices by one or more dummy gate layers. The metal layer is configured to measure, due to a change of resistance in the metal layer, a temperature of the plurality of active area structures.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Zeng Kang, Wen-Shen Chou, Yung-Chow Peng
  • Patent number: 11898276
    Abstract: Carbon fiber and method of forming the same are provided. The method modifies proportion of a finishing oil to control a relation between a surface tension and a particle size of the finishing oil, and thus penetration of the finishing oil into an interior of the carbon fiber is avoided. Therefore, the carbon fiber can have both low oil residues and a high strength.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: February 13, 2024
    Assignee: FORMOSA PLASTICS CORPORATION
    Inventors: Kun-Yeh Tsai, Chia-Chi Hung, Wen-Ju Chou, Ching-Wen Chen, Chia-Chun Hsieh, Shi-Jie Lin, Long-Tyan Hwang
  • Patent number: 11901018
    Abstract: A local data bus of a sense amplifier associated with one bit line is used to perform logical operations for a sensing operation performed by another sense amplifier associated with a different bit line. Each sense amplifier circuit includes a sensing node that is pre-charged, then discharged through a selected memory cell and a local data bus with a number of data latches connected. Target program data can be stored in the latches and combined in logical combinations with the sensed value of the memory cell to determine whether it has verified. By including a transfer circuit between the local data buses of a pair of sense amplifiers, the logical operations of a first sense amplifier can be performed using the local data bus of the paired sense amplifier, freeing the first sense amplifier's sense node to be concurrently pre-charged for a subsequent sensing operation, thereby improving performance.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: February 13, 2024
    Assignee: SanDisk Technologies LLC
    Inventors: Iris Lu, Tai-Yuan Tseng, Chia-Kai Chou
  • Patent number: 11899269
    Abstract: A plastic barrel includes an object-end portion, an image-end portion, an inner tube portion and a plurality of protrusions. The object-end portion includes an outer object-end surface, an object-end hole and an inner annular object-end surface. One side of the inner annular object-end surface is connected to the outer object-end surface and surrounds the object-end hole. The image-end portion includes an outer image-end surface, an image-end opening and an inner annular image-end surface. The inner annular image-end surface is connected to the outer image-end surface and surrounds the image-end opening. The inner tube portion connects the object-end portion and the image-end portion and includes a plurality of inclined surfaces. The protrusions are disposed at least on one of the inner annular object-end surface, the inner annular image-end surface and the inclined surfaces, wherein the protrusions are regularly arranged around the central axis of the plastic barrel.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: February 13, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Cheng-Feng Lin, Wei-Hung Weng, Ming-Ta Chou
  • Patent number: 11901409
    Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first gate electrode disposed on the substrate and located in a first region of the semiconductor device. The semiconductor device also includes a first sidewall structure covering the first gate electrode. The semiconductor device further includes a protective layer disposed between the first gate electrode and the first sidewall structure. In addition, the semiconductor device includes a second gate electrode disposed on the substrate and located in a second region of the semiconductor device. The semiconductor device also includes a second sidewall structure covering a lateral surface of the second gate electrode.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pei-Yu Chou, Tze-Liang Lee
  • Patent number: 11903188
    Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Perng-Fei Yuh, Yih Wang, Meng-Sheng Chang, Jui-Che Tsai, Ku-Feng Lin, Yu-Wei Lin, Keh-Jeng Chang, Chansyun David Yang, Shao-Ting Wu, Shao-Yu Chou, Philex Ming-Yan Fan, Yoshitaka Yamauchi, Tzu-Hsien Yang
  • Patent number: D1014130
    Type: Grant
    Filed: July 30, 2022
    Date of Patent: February 13, 2024
    Inventor: Tser Wen Chou