Abstract: The semiconductor package substrate module including a substrate, a plurality of first wires, at least one second wire, a chip, and an encapsulating body, wherein the first wires electrically connect to a first electrical contact point of the substrate and a second electrical contact point of the chip. Besides, one end of the at least one second wire connects to the at least one grounding transfer area or a first ground contact point of the substrate, and another end of the second wire extends toward a cutting area. The encapsulating body encapsulates the substrate, the first and second wires, and the chip. The semiconductor package substrate module is cut and separated along the cutting area of the substrate to form a plurality of semiconductor packaging components. A side surface of the encapsulating body exposes the first wires or at least one second wire of each semiconductor packaging component.

Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.

Abstract: The disclosure provides an apparatus for high throughput analysis of samples and a method of making an assay card and performing an assay using the apparatus. The apparatus can include a transporter to position and advance a first plate of the QMAX card, a first dispenser to deposit a sample on the first plate, a second dispenser to dispense a reagent to contact the sample, a press to compress the sample between the first and second plates of the QMAX card into a uniformly thick layer, and an imager to image the uniformly thick layer.

Abstract: A p-GaN high-electron-mobility transistor (HEMT) includes a buffer layer stacked on a substrate, a channel layer stacked on the buffer layer, a supply layer stacked on the channel layer, a doped layer stacked on the supply layer, and a hydrogen barrier layer covering the supply layer and the doped layer. A source and a drain are electrically connected to the channel layer and the supply layer, respectively. A gate is located on the doped layer. The hydrogen barrier layer is doped with fluorine.

Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

Abstract: A dynamic aperture module includes a blade set and a driving portion. The blade set includes a plurality of blades, which are disposed around an optical axis to form a light through hole and rotatable for adjusting the light through hole. The driving portion includes a rotating element, at least one magnet and at least one coil. The rotating element corresponds to the blades and is configured to drive the blades to rotate, so that a dimension of the light through hole is variable. The magnet includes four polarities. The polarities of the magnet are relatively distributed along a direction surrounding the optical axis and a direction parallel to the optical axis, respectively. The coil corresponds to the magnet, and one of the magnet and the coil is disposed on the rotating element. The magnet and the coil are disposed along the direction parallel to the optical axis.

Abstract: Embodiments of the present disclosure relates to a semiconductor device structure. The structure includes a source/drain epitaxial feature disposed over a substrate, a first interlayer dielectric (ILD) disposed over the source/drain epitaxial feature, a second ILD disposed over the first ILD. The second ILD includes a first dopant species having an atomic radius equal to or greater than silicon and a second dopant species having an atomic mass less than 15. The structure also includes a first conductive feature disposed in the second ILD, and a second conductive feature disposed over the source/drain epitaxial feature, the second conductive feature extending through the first ILD and in contact with the first conductive feature.

Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.

Abstract: Systems and methods of managing creation and configuration for 5G networks, NFs and NSSIs are provided. An instantiation or configuration request received from a managed entity respectively instantiates or configures the appropriate element. For NF instantiation, when the NF has a virtualized part to be instantiated by a VNF, interaction with an NFV MANO system instantiates the VNF is followed by NF instantiation notification and MOI creation for the NF. For NF configuration, the NF is configured and notification provided thereof. For network instantiation, after reception of a network creation request, interaction with the system to instantiate a NS that realizes the network is followed by determination that a new VNF associated with the NS has been instantiated, creation of a NF (constituting the network) MOI is realized by the new VNF, and NF configuration. For NSSI creation, a NF constituting the NSSI is created and configured.

Abstract: A reciprocating friction and wear test apparatus includes a frame unit and an abrader unit. The frame unit includes a frame that has a bottom wall formed with an opening and two side walls extending upwardly from the bottom wall. The abrader unit includes an abrader fixture, an abrader, two first sensor members, and two adjustment members. The abrader fixture extends through the opening and is pivotable relative to the bottom wall. The abrader is affixed to the abrader fixture. The two first sensor members are respectively mounted to the side walls. The two adjustment members are respectively connected to the first sensor members, extend respectively through the first sensor members, extend respectively through the side walls, and are movable toward the abrader fixture to tightly abut against the abrader fixture.

Abstract: Disclosed is a system and method for communication using an efficient fiber-to-chip grating coupler with a high coupling efficiency.

Abstract: A method for manufacturing a semiconductor structure includes: forming a semiconductor device on a main region of the device substrate, the device substrate having a peripheral region surrounding the main region; forming a first filling layer on the peripheral region of the device substrate; forming a second filling layer over the first filling layer and the semiconductor device after forming the first filling layer, the second filling layer having a polishing rate different from that of the first filling layer; performing a planarization process over the second filling layer to remove a portion of the second filling layer so that a remaining portion of the second filling layer has a planarized surface opposite to the device substrate; and bonding the device substrate to a carrier substrate through the first filling layer and the remaining portion of the second filling layer.

Abstract: A method for preparing a semiconductor device, includes: forming a first dielectric structure and a second dielectric structure over a semiconductor substrate; forming a conductive material over the first dielectric structure and the second dielectric structure, wherein the conductive material extends into a first opening between the first dielectric structure and the second dielectric structure; partially removing the conductive material to form a first bit line and a second bit line in the first opening; forming a first capacitor contact and a second capacitor contact in the first dielectric structure and the second dielectric structure, respectively; forming a sealing dielectric layer over the first bit line and the second bit line such that an air gap is formed between the sealing dielectric layer and the semiconductor substrate; and forming a first capacitor and a second capacitor over the first capacitor contact and the second capacitor contact, respectively.

Abstract: A method for monitoring paging is provided. The method is performed by a user equipment (UE) and includes actions of receiving a first Physical Downlink Control Channel (PDCCH) addressed to a first Radio Network Temporary Identifier (RNTI), and stopping monitoring a second PDCCH addressed to a second RNTI if the first PDCCH includes a paging stop indicator, where the second RNTI is the same as the first RNTI.

Abstract: A system to support validation and debugging of compiled low-level instructions for a machine learning (ML) network model on an ML-specific hardware. A compiler identifies well-defined boundaries in the ML network model based on primitives used to generate low-level instructions for the hardware. The ML network model is partitioned into units/layers/sub-graphs based on the plurality of well-defined boundaries. The compiler then generates an internal representation for each of the units wherein the internal representation is mapped to components in the hardware. Each of the units is compiled into a first set to be executed on the ML-specific hardware and a second set to be executed on a second computing device. The output results from executing the two sets of low-level instructions are compared to validate the first set of low-level instructions. If the outputs do not match fully, the first set of low-level instructions is debugged and recompiled.

Abstract: A mounting system for window blinds is provided. The mounting system provides components that can be used to mount a window blind or shade. The components of the mounting system include flex brackets, mounting clips, railing devices, adjustable arms, spacers, etc. These components can be provided in different combinations to mount different types of blinds or shades to walls or ceilings, regardless of whether the wall to be mounted to is above, behind, or to the sides of the window blind.

Abstract: An optical device is provided. The optical device includes a ring waveguide and a bus waveguide. The ring waveguide includes a coupling region. The bus waveguide is disposed adjacent to and spaced apart from the coupling region of the ring waveguide. The bus waveguide includes a coupling structure corresponding to the coupling region.

Abstract: Disclosed is a DDR SDRAM signal calibration device capable of adapting to the variation of voltage and/or temperature. The device includes: an enablement signal setting circuit configured to generate data strobe (DQS) enablement setting; a signal gating circuit configured to generate a DQS enablement setting signal and a DQS enablement signal according to the DQS enablement setting and then output a gated DQS signal according to the DQS enablement signal and a DQS signal; and a calibration circuit configured to generate a first delay signal according to the DQS enablement setting signal and generate a second delay signal according to the first delay signal, the calibration circuit further configured to generate a calibration signal according to the first and second delay signals and the DQS signal. The enablement signal setting circuit maintains or adjusts the DQS enablement setting according to the calibration signal.

Abstract: Systems and methods of re-configuring PCI values for a NR cell and performing mobility robustness optimization are described. To reconfigure the PCI values. The NRM data and the PCI of candidate cells measurements are analyzed to detect a potential PCI collision or PCI confusion among NR cells. In response to detection of the potential PCI collision or confusion, a new PCI value for at least one NR cell is determined and instructions to re-configure the at least one NR cell with the new PCI value are sent to a producer of provisioning MnS. For MRO, a NF provisioning MnS with modifyMOIAttributes operation to configure MRO targets for an MRO function and to enable the MRO function for a NR cell are consumed, as is a performance assurance MnS with a notifyFileReady or reportStreamData operation to collect MRO-related performance measurements. The measurements are analyzed to evaluate MRO performance.

Abstract: A riser assembly may include a riser cage and a riser card. The riser cage includes sidewalls, a base extending from the sidewalls, and mounting features to mount the riser cage to a chassis of the electronic device. The base is coupled to the riser card positioned on a first side of the base. The base includes an opening to permit the connector to extend through the opening to protrude partially beyond the opening to a location on a second side of the base where the connector can detachably connect to an expansion card installed in the riser cage between the sidewalls. The base contacts the connector around the opening to provide lateral support to the connector on opposing faces (e.g., first sidewalls) of the connector.