Patents by Inventor Chou

Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11916125
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: February 27, 2024
    Inventors: Chih-Chao Chou, Kuo-Cheng Chiang, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang
  • Patent number: 11916100
    Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Ching-Chun Wang
  • Patent number: 11911871
    Abstract: A method of manufacturing a composite article includes providing a polishing pad; rubbing over the polishing pad to produce a polishing pad debris; collecting the polishing pad debris; providing a wood material; and applying a force over the wood material and the polishing pad debris to form the composite article, wherein the composite article includes the wood material and the polishing pad debris, and the rubbing of the polishing pad includes removing a portion of the polishing pad to produce the polishing pad debris.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hua-Chou Chiang, Chandler Ying Lai See, Chung-Chieh Ko
  • Patent number: 11917433
    Abstract: A method and system for generating performance measurements related to DL and UL packet delays through a NG-RAN are described. The NG-RAN receives GTP PDU monitoring packets from a UPF and, in response measures the DL delays of the packets to and UL delays from a UE. The NG-RAN determines the per 5QI and per S-NSSAI distribution of the DL and UL delays and sends the performance measurements to a service provider. The average DL and UL delays may also be provided to the service provider. The service provider is in the NG-RAN or a separate management system. For a network slice, service providers for different NG-RANs send the performance measurements to a network slice service provider, where the individual NG-RAN performance measurements are combined to provide both the average and distribution of the DL and UL delays in the network slice.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: February 27, 2024
    Assignee: Intel Corporation
    Inventors: Yizhi Yao, Joey Chou
  • Patent number: 11912816
    Abstract: A polymer and a light-emitting device employing the same are provided. The polymer includes a first repeat unit with a structure represented by Formula (I): wherein the definitions of R1, R2, A1, A2, A3, and Z1 and n are as defined in the specification. At least one of A1, A2, and A3 is not hydrogen.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: February 27, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chin-Hui Chou, Han-Cheng Yeh, Jia-Lun Liou, Mei-Rurng Tseng
  • Patent number: 11916126
    Abstract: A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer a titanium aluminide layer, and a middle layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and the middle layer is disposed between the titanium aluminide layer and the titanium nitride barrier layer. The middle layer is directly connected with the titanium aluminide layer and the titanium nitride barrier layer, and the middle layer includes titanium and nitrogen. A concentration of nitrogen in the middle layer is gradually decreased in a vertical direction towards an interface between the middle layer and the titanium aluminide layer.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: February 27, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Hsin Hsu, Huan-Chi Ma, Chien-Wen Yu, Shih-Min Chou, Nien-Ting Ho, Ti-Bin Chen
  • Patent number: 11914429
    Abstract: An electronic device includes a host, a display, a sliding plate, and a keyboard. The host has an operating surface. The display is pivoted to the host. The sliding plate is slidably disposed in the host, where the display is mechanically coupled to the sliding plate, and the sliding plate includes a plat portion and a recess portion that are arranged side by side. The keyboard is integrated to the host. The keyboard includes a key structure, where the key structure includes a key cap and a reciprocating element, and the key cap is exposed from the operating surface of the host. The reciprocating element is disposed between the key cap and the sliding plate and has a first end connected to the key cap and a second end contacting the sliding plate. The second end is located on a sliding path of the plat portion and the recess portion.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: February 27, 2024
    Assignee: Acer Incorporated
    Inventors: Hung-Chi Chen, Shun-Bin Chen, Huei-Ting Chuang, Yen-Chieh Chiu, Yu-Wen Lin, Yen-Chou Chueh, Po-Yi Lee
  • Patent number: 11913440
    Abstract: A fixing device of a motor of an air compressor contains: a body, a cylinder, a motor, a transmission mechanism, and at least one retainer. The body includes a first positioning orifice and a second positioning orifice. The cylinder is connected on the body. The motor is fixed on the body, a small gear is received in the first positioning orifice and is connected on the motor, and a connection seat of the motor is accommodated in the first orifice. The transmission mechanism actuates a piston to move in the cylinder reciprocately. The at least one retainer is configured to fix the body and the motor. A first end of at least one retainer is engaged on the body, and a second end of the at least one retainer is engaged on the motor so that the motor is fixed on the body without using any screws.
    Type: Grant
    Filed: May 8, 2022
    Date of Patent: February 27, 2024
    Inventors: Wen-San Chou, Cheng-Hsien Chou
  • Patent number: 11914217
    Abstract: An imaging lens assembly has an optical axis, and includes a plastic carrier element and an imaging lens element set. The plastic carrier element includes an object-side surface, an image-side surface, an outer surface and an inner surface. The object-side surface includes an object-side opening. The image-side surface includes an image-side opening. The inner surface is connected to the object-side opening and the image-side opening. The imaging lens element set is disposed in the plastic carrier element, and includes at least three lens elements, each of at least two adjacent lens elements of the lens elements includes a first axial assembling structure, the first axial assembling structures are corresponding to and connected to each other. A solid medium interval is maintained between the adjacent lens elements and the inner surface. The solid medium interval is directly contacted with the adjacent lens elements and the inner surface.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: February 27, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Jyun-Jia Cheng, Lin-An Chang, Ming-Ta Chou, Cheng-Feng Lin
  • Patent number: 11915977
    Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chih-Hui Huang, Sheng-Chau Chen, Shih Pei Chou, Chia-Chieh Lin
  • Patent number: 11913049
    Abstract: An engineered microorganism(s) with novel pathways for the conversion of short-chain hydrocarbons to fuels and chemicals (e.g. carboxylic acids, alcohols, hydrocarbons, and their alpha-, beta-, and omega-functionalized derivatives) is described. Key to this approach is the use of hydrocarbon activation enzymes able to overcome the high stability and low reactivity of hydrocarbon compounds through the cleavage of an inert C—H bond. Oxygen-dependent or oxygen-independent activation enzymes can be exploited for this purpose, which when combined with appropriate pathways for the conversion of activated hydrocarbons to key metabolic intermediates, enables the generation of product precursors that can subsequently be converted to desired compounds through established pathways. These novel engineered microorganism(s) provide a route for the production of fuels and chemicals from short chain hydrocarbons such as methane, ethane, propane, butane, and pentane.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: February 27, 2024
    Inventors: Ramon Gonzalez, James Clomburg, Alexander Chou
  • Patent number: 11917436
    Abstract: A base station (BS) and a method for wireless communication are provided. The method includes transmitting a first radio resource control (RRC) configuration that configures a radio link monitoring configuration that includes a beam failure detection (BFD) timer and a beam failure indication (BFI) count threshold. The first RRC configuration enables a user equipment (UE) to: start or restart the BFD timer by a medium access control (MAC) entity of the UE each time a BFI is received from a lower layer; and initiate a beam failure recovery (BFR) procedure upon determining that the number of the received BFIs is greater than or equal to the BFI count threshold. The method further includes transmitting a second RRC configuration that reconfigures the radio link monitoring configuration. The second RRC configuration enables the UE to set the BFI counter to zero in response to receiving the second RRC configuration.
    Type: Grant
    Filed: March 7, 2023
    Date of Patent: February 27, 2024
    Assignee: FG Innovation Company Limited
    Inventors: Chia-Hung Wei, Chie-Ming Chou
  • Patent number: 11914940
    Abstract: A semiconductor device includes an edge active cell, an inner active cell and a middle active cell. The edge active cell is located near an edge of the semiconductor device. The edge active cell includes a plurality of fingers. The inner active cell is adjacent to the edge active cell toward a central portion of the semiconductor device. The inner active cell includes a plurality of fingers and at least one of the plurality of fingers of the edge active cell is electrically connected to at least one of the plurality of fingers of the inner active cell. The middle active cell is located near the central portion of the semiconductor device. The middle active cell includes a plurality of fingers and each of the fingers of the middle active cell is electrically connected to each other.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jaw-Juinn Horng, Wen-Shen Chou, Yung-Chow Peng
  • Patent number: 11911446
    Abstract: The present disclosure provides for use of variants of C-type natriuretic peptide (CNP), and novel pharmaceutical compositions and formulations comprising CNP variant peptides for the treatment of skeletal dysplasias, one or more symptoms of skeletal dysplasias, such as long bone growth or growth velocity, and other disorders having a skeletal dysplasia and/or CNP-associated symptom or component.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: February 27, 2024
    Assignee: BIOMARIN PHARMACEUTICAL INC.
    Inventors: Sherry Bullens, Stuart Bunting, Tianwei Chou, Augustus O. Okhamafe, Christopher P. Price, Daniel J. Wendt, Clarence Yap
  • Patent number: 11916077
    Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
  • Patent number: 11914265
    Abstract: In an embodiment, a phase shifter includes: a light input end; a light output end; a p-type semiconductor material, and an n-type semiconductor material contacting the p-type semiconductor material along a boundary area, wherein the boundary area is greater than a length from the light input end to the light output end multiplied by a core width of the phase shifter.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huan-Neng Chen, Chewn-Pu Jou, Lan-Chou Cho, Feng-Wei Kuo
  • Patent number: 11917445
    Abstract: A method performed by a BS for CHO is provided. The method includes transmitting a CHO command to a UE, the CHO command including a CHO command ID and a measurement ID associated with the CHO command ID; causing the UE to execute the CHO command to handover to a target BS when a trigger condition associated with the measurement ID is fulfilled; causing the UE to forgo transmitting the measurement report during the execution of the CHO command despite the UE being configured, via a report configuration associated with the measurement ID, to transmit the measurement report; transmitting, to the UE, a message that causes the UE to remove the CHO command; and after transmitting the message to the UE, determining that the report configuration is removed by the UE without transmitting, to the UE, an instruction to remove the report configuration.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: February 27, 2024
    Assignee: FG Innovation Company Limited
    Inventors: Hung-Chen Chen, Yung-Lan Tseng, Mei-Ju Shih, Chie-Ming Chou
  • Patent number: 11917527
    Abstract: An apparatus for a Non-Real-Time RAN Intelligent Controller (Non-RT RIC) of a Service Management and Orchestration (SMO) entity of an Open Radio Access Network (O-RAN) includes processing circuitry coupled to memory. To configure the Non-RT RIC for allocation of network slice subnet instance (NSSI) resources in the O-RAN, the processing circuitry is to collect performance measurements related to usage of the NSSI resources. An artificial intelligence (AI)/machine learning (ML) model is trained based on the performance measurements. The allocation of the NSSI resources is optimized at a time determined by an inference of the AI/ML model.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: February 27, 2024
    Assignee: Intel Corporation
    Inventor: Joey Chou
  • Patent number: 11915754
    Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Der Chih, Chung-Cheng Chou, Wen-Ting Chu
  • Publication number: 20240063125
    Abstract: Nanostructure field-effect transistors (nano-FETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a power rail, a dielectric layer over the power rail, a first channel region over the dielectric layer, a second channel region over the first channel region, a gate stack over the first channel region and the second channel region, where the gate stack is further disposed between the first channel region and the second channel region and a first source/drain region adjacent the gate stack and electrically connected to the power rail.
    Type: Application
    Filed: November 1, 2023
    Publication date: February 22, 2024
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Chih-Chao Chou, Wen-Ting Lan, Chih-Hao Wang