Abstract: A method for a user equipment (UE) monitoring a physical downlink control channel (PDCCH) for power saving signaling is disclosed. The method comprises receiving a discontinuous reception (DRX) configuration from a base station (BS) to configure the UE to monitor a scheduling signal on the PDCCH within a DRX active time, and receiving a configuration from the BS to configure the UE to monitor the power saving signaling on the PDCCH and instructing the UE to wake up for monitoring the scheduling signal in the DRX active time, wherein the configuration includes a time in milliseconds prior to a start of a DRX on-duration time, and instructs the UE to start monitoring the PDCCH for the power saving signaling.

Abstract: The disclosure is directed to a timing controller having a mechanism for frame synchronization, a display panel having the timing controller thereof, and a display system having the timing controller thereof. According to an aspect of the disclosure, the disclosure provides an integrated circuit which includes a timing controller to transmit a first TE signal to an application processor and receive a first image frame from the application processor after the application processor receives the first TE signal, and a control circuit to generate a first sync signal when the timing controller receives the first image frame, wherein when the application processor receives a second TE signal and the application processor is not ready to transmit a second image frame to the timing controller, the control circuit delays a first waiting period to generate a second sync signal.

Abstract: A semiconductor structure and method of forming a semiconductor structure are provided. In some embodiments, the method includes forming a gate structure over a substrate. An epitaxial source/drain region is formed adjacent to the gate structure. A dielectric layer is formed over the epitaxial source/drain region. An opening is formed, the opening extending through the dielectric layer and exposing the epitaxial source/drain region. Sidewalls of the opening are defined by the dielectric layer and a bottom of the opening is defined by the epitaxial source/drain region. A silicide layer is formed on the epitaxial source/drain region. A metal capping layer including tungsten, molybdenum, or a combination thereof is selectively formed on the silicide layer by a first deposition process. The opening is filled with a first conductive material in a bottom-up manner from the metal capping layer by a second deposition process different from the first deposition process.

Abstract: A conduit system for transporting gas from a gas containing chamber for processing a substrate from which semiconductor devices are formed includes a liner with a spiral vent. The conduit system utilizes a curtain of gas to prevent or reduce deposition of material onto an inner surface of the conduit transporting the gas from the gas containing chamber.

Abstract: A heat pipe is provided as an electrically inactive structure to dissipate heat that is generated by vertically stacked field effect transistors (FETs). The heat pipe is present in an electrically inactive device area which is located adjacent to an electrically active device area that includes the vertically stacked FETs.

Abstract: A backlight module and a display apparatus are provided. The backlight module includes a quantum fluorescent film. The quantum fluorescent film includes a light conversion layer. The light conversion layer includes a resin material, a plurality of quantum dots and a plurality of phosphors. The plurality of quantum dots and the plurality of phosphors are dispersed in the resin material.

Abstract: A microelectronic structure including a plurality of lower transistors and a plurality of upper transistors, where channels of the upper transistors are staggered from channels of the lower transistors. A lower dielectric pillar located beneath an upper transistor, where the dielectric pillar separates bottom transistors.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming a contact etch stop layer (CESL) on the gate structure, forming an interlayer dielectric (ILD) layer on the CESL, forming a contact plug in the ILD layer and adjacent to the gate structure, forming a first stop layer on the ILD layer, and removing the first stop layer and the ILD layer around the gate structure to form an air gap exposing the CESL.

Abstract: A method for manufacturing ultra-thin glass substrates and a method for manufacturing a display panel are provided, including: providing a glass base material preset with n substrate areas and a skeleton area surrounding the substrate areas, wherein n is greater than or equal to 1; at least forming an etching protection layer, wherein, each etching protection layer includes a main area and at least one thinned area extending along a preset bending path; at least etching the skeleton area of the glass base material to separate the substrate areas from the glass base material, forming at least one bending stress dissipation groove, and forming a stress dissipation edge along an edge of each substrate area; removing the etching protection layer to get independent glass substrates having the bending stress dissipation groove. The method improves bending performance along the preset bending path.

Abstract: Some implementations described herein provide a semiconductor device having an oxide-filled barrier structure between structures of gate-all-around transistors included in the semiconductor device. The use of the oxide-filled barrier structure may reduce a distance separating nanosheet structures of a p-type metal-oxide semiconductor fin structure and an n-type metal-oxide semiconductor fin structure, broaden an availability of work-function metals for gate structures formed around nanochannels of the p-type metal-oxide semiconductor fin structure and n-type metal-oxide semiconductor structure, and improve a performance of the gate-all-around transistors by reducing miller capacitances of the gate-all-around transistors. Furthermore, the oxide-filled barrier structure may enable the combining of the p-type metal-oxide semiconductor fin structure and the n-type metal-oxide semiconductor fin structure to form a type of integrated circuitry, such as an inverter.

Abstract: A casing assembly includes a frame, a support member, and an elastic holder, where the frame includes a frame bottom plate and a partition, the partition is disposed on the frame bottom plate and includes an engagement structure located at a side of the partition located away from the frame bottom plate, the support member is disposed on the frame bottom plate, and the elastic holder is disposed on the frame bottom plate and includes a holding structure movable with respect to the frame bottom plate.

Abstract: A double-end laser rangefinder includes a ranging board, a control board, a key board which are integrated to form a mainboard. Two lens mounting bases are coaxially mounted at two ends of a main frame. First end and second end with lens-mounting bases are coaxially mounted in the main frame. Two lens groups are mounted on the two lens-mounting bases respectively. Each lens group includes a transmitting lens and a receiving lens. The receiving lenses on the first end and the second end are coaxial, the transmitting lenses on the first end and the second end are also coaxial. Coaxial arrangement of light paths of the two transmitting lenses and the two receiving lenses is realized through the main frame.

Abstract: The present invention is related to, among other things, the devices and methods that improve the accuracy and reliability of an assay, even when the assay device and/or the operation of the assay device has certain errors, and in some embodiments, the errors are random. One aspect of the present invention is to overcome the random errors or imperfections of an assay device or the operation of the assay device by measuring, in addition to measuring the analyte in a sample to generate an analyte test result, the trustworthiness of the analyte test result. The analyte test result will be reported, only when the trustworthiness meets a predetermined threshold, otherwise the analyte test result will be discarded. Various of parameter variation have been used for test trustworthy determination.

Abstract: Drug delivery devices, sealing members for containers housed within such drug delivery devices, and related methods of assembly are disclosed. The drug delivery device may include a housing, a container disposed in the housing and having an interior volume, a drug disposed in the interior volume, and a septum. The container may have an opening formed in an end surface and which communicates with the interior volume. The septum may include a proximal end inserted through the opening into the interior volume of the container. Additionally, the septum may include a distal end having a flange disposed outwardly of the proximal end and contacting the end surface of the container. At least an end portion of the flange may be made of a material that is permeable to a gaseous sterilizing agent.

Abstract: A package structure and a manufacturing thereof are provided. The package structure includes a base, a chip, a control element and an underfill. The chip is disposed on the base and includes a recess, and the recess has a bottom surface and a sidewall. The control element is disposed between the base and the chip and disposed on the bottom surface of the recess, and a gap exists between the control element and the sidewall of the recess. The underfill is disposed in the recess. The chip and the control element are electrically connected to the base respectively.

Abstract: An imaging lens assembly module includes an imaging lens element set, a lens carrier and a light blocking structure. The imaging lens element set has an optical axis. At least one lens element of the lens elements is disposed in the lens carrier. The light blocking structure includes a light blocking opening. The optical axis passes through the light blocking opening, and the light blocking opening includes at least two arc portions and a shrinking portion. Each of the arc portions has a first curvature radius for defining a maximum diameter of the light blocking opening. The shrinking portion is connected to the arc portions for forming the light blocking opening into a non-circular shape. The shrinking portion includes at least one protruding arc which extends and shrinks gradually from the shrinking portion to the optical axis, and the protruding arc has a second curvature radius.

Abstract: A semiconductor package includes a substrate having thereon at least an antenna layer and a ground reflector layer under the antenna layer, a radio frequency (RF) die disposed on or in the substrate, a molding compound disposed on the antenna layer of the substrate, and a frequency-selective surface (FSS) structure disposed on the molding compound. The FSS structure is a two-dimensional periodic array of metal patterns of same shape and size. The FSS structure has highly reflective characteristic.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.

Abstract: Methods and associated devices including the fabrication of a semiconductor structure are described that include epitaxially growing a stack of layers alternating between a first composition and a second composition. The stack of layers extends across a first region and a second region of a semiconductor substrate. The stack of layers in the second region of the semiconductor substrate may be etched to form an opening. A passivation process is then performed that includes introducing chlorine to at least one surface of the opening. After performing the passivation process, an epitaxial liner layer is grown in the opening.