Patents by Inventor Chou

Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11862675
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Karthick Murukesan, Wen-Chih Chiang, Chun Lin Tsai, Ker-Hsiao Huo, Kuo-Ming Wu, Po-Chih Chen, Ru-Yi Su, Shiuan-Jeng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
  • Patent number: 11863373
    Abstract: A method, performed by a User Equipment (UE), for a Beam Failure Recovery (BFR) procedure includes receiving, from a Base Station (BS), a BFR configuration for a serving cell of the BS, wherein the BFR configuration includes a threshold for a Beam Failure Instance (BFI) counter associated with the serving cell, and the threshold is associated with a beamFailureInstanceMaxCount information element (IE); incrementing a value of the BFI counter based on a Beam Failure Detection (BFD); triggering the BFR procedure for the serving cell when the value of the BFI counter is equal to or higher than the threshold; performing Band Width Part (BWP) switching for the serving cell when receiving a reconfiguration indication from the BS, wherein the reconfiguration indication includes a BWP index; and setting the value of the BFI counter to zero when performing the BWP switching.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: January 2, 2024
    Assignee: FG Innovation Company Limited
    Inventors: Hsin-Hsi Tsai, Chia-Hung Wei, Heng-Li Chin, Chie-Ming Chou
  • Patent number: 11862835
    Abstract: The present invention discloses a dielectric filter with multilayer resonator, including a dielectric block, a plurality of multilayer resonator formed in the dielectric block, wherein each multilayer resonator is in a column shape extending in a first direction into the dielectric block and is formed of multiple metal layers paralleling and overlapping each other in a second direction, and vias extend in the second direction and connecting the metal layers in each multilayer resonator, and a ground electrode connected to the ground terminal of each multilayer resonator.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: January 2, 2024
    Assignee: CYNTEC CO., LTD.
    Inventors: Sheng-Ju Chou, Chen-Chung Liu
  • Patent number: 11862538
    Abstract: In some examples a semiconductor chip package includes a conductive terminal. In addition, the semiconductor chip package includes a die pad including a top side and a recess extending into the top side. The die pad is downset relative to the conductive terminal. Further, the semiconductor ship package includes a semiconductor die positioned within the recess, wherein the semiconductor die has an outer perimeter, and a solder fillet engaged within the recess and with the outer perimeter of the semiconductor die. Still further, the semiconductor chip package includes a wire bond coupled to the semiconductor die and the conductive terminal, and a mold compound covering the conductive terminal, the wire bond, the die pad, and the semiconductor die.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 2, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chung-Hao Lin, Hung-Yu Chou, Bo-Hsun Pan, Dong-Ren Peng, Pi-Chiang Huang, Yuh-Harng Chien
  • Patent number: 11862650
    Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Chien Yu, Ting-Cheng Chang, Wen-Hau Wu, Chih-Kung Chang
  • Patent number: 11859237
    Abstract: A method for sizing a DNA molecule is disclosed, which comprises the following steps of: providing a DNA sizing device, comprising: a cover substrate; a substrate disposed on the cover substrate and comprising a first hole and a second hole; and a first slit-like channel disposed between the cover substrate and the substrate, wherein two ends of the first slit-like channel respectively connects to the first hole and the second hole; loading a sample comprising a DNA molecule to the first slit-like channel through the first hole, wherein the DNA molecule moves in a direction from the first hole to the second hole; detecting and recording an intensity and an area of a distribution of the DNA molecule; and analyzing the intensity and the area to obtain the size of a DNA molecule.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: January 2, 2024
    Assignee: ACADEMIA SINICA
    Inventors: Chia-Fu Chou, Jia-Wei Yeh, Yii-Lih Lin
  • Patent number: 11861928
    Abstract: Optical sensors and their making methods are described herein. In some embodiments, a described sensing apparatus includes: an image sensor; a collimator above the image sensor, wherein the collimator includes an array of apertures; and an optical filtering layer above the collimator, wherein the optical filtering layer is configured to filter a portion of light to be transmitted into the array of apertures.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: You-Cheng Jhang, Han-Zong Pan, Wei-Ding Wu, Jiu-Chun Weng, Hsin-Yu Chen, Cheng-San Chou, Chin-Min Lin
  • Patent number: 11864092
    Abstract: Techniques for performance measurements related to application triggering and short message service (SMS) over non-access stratum (NAS) including obtaining raw performance measurements from one or more network functions in a wireless communication network, the one or more network functions including at least one of a network exposure function (NEF) or an access and mobility management function (AMF), and generating performance measurements for the one or more network functions based on the raw performance measurements.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: January 2, 2024
    Assignee: Apple Inc.
    Inventors: Yizhi Yao, Joey Chou
  • Patent number: 11862654
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor, and a method for forming the image sensor, in which an inter-pixel trench isolation structure is defined by a low-transmission layer. In some embodiments, the image sensor comprises an array of pixels and the inter-pixel trench isolation structure. The array of pixels is on a substrate, and the pixels of the array comprise individual photodetectors in the substrate. The inter-pixel trench isolation structure is in the substrate. Further, the inter-pixel trench isolation structure extends along boundaries of the pixels, and individually surrounds the photodetectors, to separate the photodetectors from each other. The inter-pixel trench isolation structure is defined by a low-transmission layer with low transmission for incident radiation, such that the inter-pixel trench isolation structure has low transmission for incident radiation.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Keng-Yu Chou, Wei-Chieh Chiang, Chin-Chia Kuo, Wen-Hau Wu, Hua-Mao Chen, Chih-Kung Chang
  • Patent number: 11862842
    Abstract: Provided is a display apparatus including a display panel, multiple antenna electrodes, a dummy electrode, and multiple feed lines. The display panel has a display area. The antenna electrodes are disposed on the display panel and overlap the display area. The dummy electrode is disposed around the antenna electrodes and overlaps the display area. The dummy electrode is electrically separated from the antenna electrodes, and has multiple dummy wire segments whose extension directions intersect each other. The dummy wire segments have multiple breaks. The feed lines are respectively electrically connected to the antenna electrodes. An antenna module is also provided.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: January 2, 2024
    Assignee: Au Optronics Corporation
    Inventors: Chen-Yi Chang, Chao-Wei Yeh, Yu-Ling Yeh, Pei-Heng Li, Chao-Yang Chou, Hsi-Tseng Chou
  • Patent number: 11859262
    Abstract: Disclosed in this application are a large-sized high-Nb superalloy ingot and a smelting process thereof. The smelting process includes: vacuum induction melting to prepare a plurality of vacuum induction melting ingots with the same composition which are used for preparing electroslag electrodes with the same number as the vacuum induction melting ingots for use in electroslag remelting, preparing a consumable electrode from the prepared consumable electroslag electrodes, and performing vacuum consumable arc remelting for a plurality of times by using the consumable electroslag electrodes as raw material. A large-sized high-Nb superalloy ingot having a weight of 15 tons or above and a diameter of 800 mm or above can be prepared from such process.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: January 2, 2024
    Assignees: Gaona Aero Material Co., Ltd., Fushun Special Steel Shares Co., Ltd.
    Inventors: Shuo Huang, Guangpu Zhao, Beijiang Zhang, Ran Duan, Heyong Qin, Lianpeng Li, Yingyu Chou, Chao Qi
  • Publication number: 20230417822
    Abstract: The present invention discloses an RF element group testing system and method. The method comprises steps: adding an identification feature to a first RF signal, which is output by one of the plurality of tested RF elements, to generate an identification RF signal; synthesizing the identification RF signal and a second RF signal, which is output by each of the rest of the tested RF elements, to generate a corresponding synthesis signal; resolving the synthesis signal into the identification RF signal and the corresponding second RF signal according to the identification feature; restoring the identification RF signal into the first RF signal; and calculating at least one signal-feature parameter of the first RF signal and the second RF signal.
    Type: Application
    Filed: June 20, 2023
    Publication date: December 28, 2023
    Inventors: CHIH-YUAN CHU, HSI-TSENG CHOU, JAKE WALDVOGEL LIU, CHIH-WEI CHIU
  • Publication number: 20230420688
    Abstract: Provided are an electrolytic copper foil, an electrode and a lithium-ion cell comprising the same. The electrolytic copper foil has a first surface and a second surface opposite the first surface. An absolute difference of the FWHM of the characteristic peaks of (111) planes of the first surface and the second surface analyzed by GIXRD is less than 0.14, the first and the second surfaces each have a nanoindentation hardness of 0.3 GPa to 3.0 GPa, and the yield strength of the electrolytic copper foil is more than 230 MPa. By controlling the absolute difference of the FWHM of the characteristic peaks of (111) plane of these two surfaces, the nanoindentation hardness of these two surfaces and the yield strength, the electrolytic copper foil can have improved tolerance to the repeated charging and discharging and reduced warpage, thereby improving the yield rate and value of the lithium-ion cell.
    Type: Application
    Filed: September 8, 2022
    Publication date: December 28, 2023
    Inventors: Ting-Mu CHUANG, SUNG-SHIUAN LIN, Yao-Sheng LAI, Jui-Chang CHOU
  • Publication number: 20230420640
    Abstract: Provided are an electrolytic copper foil, an electrode and a lithium-ion cell comprising the same. The electrolytic copper foil has a first surface and a second surface, which are analyzed by grazing incidence X-ray diffraction (GIXRD), and each have an intensity of a characteristic peak of (111) plane denoted by I1, an intensity of a characteristic peak of (200) plane denoted by I2, an intensity of a characteristic peak of (220) plane denoted by I3, an FWHM of the characteristic peak of (111) plane denoted by W1, and an FWHM of the characteristic peak of (200) plane denoted by W2. The first and second surfaces each have a ratio of (I1+I2)/(I1+I2+I3) of 0.83 or more and a value of (W1+W2) of 0.80 or less. By controlling the features, it can improve the corrosion resistance of the electrolytic copper foil and further increase the safety of the lithium-ion cell.
    Type: Application
    Filed: October 4, 2022
    Publication date: December 28, 2023
    Inventors: Chih-Chung WU, Yao-Sheng LAI, Jui-Chang CHOU
  • Publication number: 20230420504
    Abstract: A high-voltage transistor may include a planar active region for a first source/drain active region, a second source/drain active region, and/or a channel active region. The planar active region(s) are included instead of a plurality of fin active regions to reduce the amount of surface area of the active regions in the high-voltage transistor that is in contact with surrounding dielectric layers of the high-voltage transistor. In other words, the planar active region(s) reduce the interface surface area between the silicon-based active regions of the high-voltage transistor and the surrounding oxide-based dielectric layers. The reduced interface surface area may reduce the occurrence of charge trapping in the high-voltage transistor, which may result in increased performance stability for the high-voltage transistor and/or may provide increased operational lifetime of the high-voltage transistor.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Inventors: Wan-Jyun SYUE, Hsueh-Liang CHOU, Yi-Jen LO
  • Publication number: 20230417342
    Abstract: The present invention provides a flow control switch including a pipeline structure, a rotating structure, a position-limiting structure and a knob structure. The pipeline structure includes a tubular body and a ball body rotatably disposed in the tubular body. The rotating structure includes a rotatable element connected to the ball body for driving the ball body to rotate. The position-limiting structure is disposed on the tubular body. The knob structure is liftably disposed on the rotating structure for cooperating with the rotatable element. The position-limiting structure has a first and a second position-limiting groove. The knob structure includes a knob body liftably disposed on the rotatable element and a position-limiting element detachably disposed on the knob body. The position-limiting element is optionally disposed in one of the first and the second position-limiting groove, so as to limit a rotation of the rotatable element relative to the position-limiting structure.
    Type: Application
    Filed: May 30, 2023
    Publication date: December 28, 2023
    Inventors: KU-HUA CHOU, YEN-CHENG CHEN, SHIH WEI YU
  • Publication number: 20230415430
    Abstract: A thermoplastic composite material has an inner layer material and at least one layer of outer layer material. The inner layer material is a core layer that contains fiber bundles, a first thermoplastic resin and a first auxiliary agent; and the at least one layer of outer layer material wraps the core layer and is a resin layer comprising a second thermoplastic resin and an optional second auxiliary agent. The fiber bundles extend continuously from one end of the core layer to the opposite end thereof. The inner layer-outer layer composite structure, can effectively improves the processing performance of the thermoplastic composite material and the lubricity between fibers and resin matrixes during injection molding, and improves the fluidity of the fibers in a resin matrix melt.
    Type: Application
    Filed: October 30, 2021
    Publication date: December 28, 2023
    Inventors: Dali GAO, Changjin LI, Shijun ZHANG, Kai XU, Peng KANG, Qi ZHANG, Hua YIN, Mingfu LV, Dehui KONG, Qi XIN, Tao CAI, Mu DONG, Jingbo SHAO, Hongwei SHI, Changhui SUN, Yiqing BAI, Yigang TAN, Guang LI, Xiaoyong GAO, Jinqi HE, Meijie LI, Meng XU, Baige CHOU, Yun LV, Yueming REN
  • Publication number: 20230416362
    Abstract: Antibodies and antigen-binding fragments that bind to TIGIT are disclosed. The disclosure further relates to methods and compositions for use in treating an immune-related disease (e.g., a cancer or an infection or infectious disease) by administering a composition disclosed herein.
    Type: Application
    Filed: May 17, 2023
    Publication date: December 28, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Min-Yuan CHOU, Li-Tsen LIN, Chung-Yuan SUN, Ya-Ping LAI, Chin-Pen LAI, Ssu-Yuan WU, Mei-Wei LIN
  • Publication number: 20230419872
    Abstract: A display detection device includes a panel, a detection board, and a detection adapter board. The panel is configured to display. The detection board is coupled to the panel, and is configured to input a detection signal. The detection adapter board is coupled to the panel, and is configured to respond to the detection signal to generate a detection result.
    Type: Application
    Filed: December 29, 2022
    Publication date: December 28, 2023
    Inventors: Te-Sheng CHEN, June-Woo LEE, Bo-Kai LIAO, Mei-Yi Li, Yu-Chieh KUO, Chun-Chang HUNG, Shang-Chieh CHOU, You-Ru LYU, Yu-Hsun LIN, Chun-Shuo CHEN
  • Patent number: D1009851
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: January 2, 2024
    Assignee: ASUSTek COMPUTER INC.
    Inventor: Ching Chou