Abstract: A dual-mode fluid connector includes: a hollow connecting element, comprising a chamber inside the hollow connecting element; a material tube, positioned on the hollow connecting element and connected through the camber; a cleaning tube, positioned on the hollow connecting element and connected through the camber; a head portion, positioned on one terminal of the hollow connecting element and having a connecting opening, wherein the connecting opening can be detachably connected to a material container; a rear portion, positioned on another terminal of the hollow connecting element and having a through hole; and a rod, inserted into the chamber via the through hole.

Abstract: A connector unit includes a contact module received within an insulative housing. The contact module includes an upper contact unit and a lower contacts unit stacked with each other. Each of the upper contact unit and the lower contact unit includes a front/outer contact part and a rear/inner contact part each including plural contacts integrally formed with plural insulative transverse bars via insert-molding. The contacts include plural differential pair signal contacts and plural grounding contacts alternately arranged with each other along a transverse direction. Plural grounding bars are attached to corresponding transverse bars, respectively, wherein each grounding bar include plural tabs mechanically and electrically connecting to the corresponding grounding contacts. Each grounding bar is equipped with a plastic attachment tie bar to cooperate with a corresponding transverse bar to sandwich the grounding bar therebetween for securement.

Abstract: Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.

Abstract: The present disclosure provides systems and methods for sorting a cell. The system may comprise a flow channel configured to transport a cell through the channel. The system may comprise an imaging device configured to capture an image of the cell from a plurality of different angles as the cell is transported through the flow channel. The system may comprise a processor configured to analyze the image using a deep learning algorithm to enable sorting of the cell.

Abstract: A semiconductor wafer defect detection system captures test images of a semiconductor wafer. The system analyzes the test images with an analysis model trained with a machine learning process. The analysis model generates simulated integrated circuit layouts based on the test images. The system detects defects in the semiconductor wafer by comparing the simulated integrated circuit layouts to reference integrated circuit layouts.

Abstract: A photographing module includes an imaging lens assembly. The imaging lens assembly includes a plurality of lens elements, wherein one of the lens elements is a plastic lens element. At least one surface of an object-side surface and an image-side surface of the plastic lens element includes an effective optical portion and a peripheral portion. The peripheral portion surrounds the effective optical portion, and includes a plurality of rib structures, a first fitting section and an isolation section. Each of the rib structures has a strip shape along a radial direction of an optical axis of the imaging lens assembly, and the rib structures are arranged around the effective optical portion. The first fitting section surrounds the effective optical portion, and is connected to another one of the lens elements adjacent to the surface. The isolation section is disposed between the rib structures and the first fitting section.

Abstract: An imaging lens system has an optical axis and includes a plastic lens barrel and an imaging lens assembly disposed in the plastic lens barrel. The plastic lens barrel surrounds the optical axis and includes an object-side surface, an image-side surface, an inner annular portion and an outer annular portion. The object-side and image-side surfaces are oppositely disposed and substantially perpendicular to the optical axis. The inner and outer annular portions are connected to the object-side and image-side surfaces. The inner annular portion has an inner parallel annular surface, and the outer annular portion has a first outer annular surface and a gate trace. The imaging lens assembly includes a plurality of imaging lens elements. One of the imaging lens elements has an outer diameter larger than ?2 millimeters. The one of the imaging lens elements has an outer edge in physical contact with the inner parallel annular surface.

Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.

Abstract: Techniques for processing data in accordance with semi-persistent scheduling include receiving, in accordance with a mechanism for automatic retransmission of undelivered data, one or more transmissions and/or retransmissions of data associated with a periodically-scheduled occasion (402, 802), failing to recover data from the (re)transmissions (405, 808), and persisting the (re)transmission payload(s) (e.g., in a combined form) in a buffer corresponding to the occasion for use in future attempts at recovering the data (412, 812), e.g., persisting the payload(s) over a length of time greater than a periodicity of the occurrences of the occasion. For example, the UE may utilize a retransmission timer (412) which, while activated, prevents the persisted payload information from being overwritten or cleared, and/or the UE may reallocate the persisted payload information from being maintained in the buffer initially associated with occasion to being maintained/persisted in another buffer (812).

Abstract: Provided is an image sensor and a method of forming the same. The image sensor includes a first substrate having a first surface and a second surface opposite to each other; a plurality of photodetectors, disposed in the first substrate; and a plurality of color filters, disposed on the second surface of the first substrate and respectively corresponding to the plurality of photodetectors. The plurality of color filters are composed of a plurality of PIN diodes, and the plurality of PIN diodes are configured to absorb light of different wavelength ranges by applying different bias voltages.

Abstract: Provided is a light-emitting quantum dot coated with at least one blue-light absorption layer, including an alloy type core consisting of Cd, Se, Zn, and S, a first shell layer having a zinc blende structure and being coated on the surface of the alloy core, and at least one second shell layer having a wurtzite structure and being coated on a surface of the first shell layer, wherein the element ratio of each of Zn and S accounts for 30 to 50% of the overall core, and the content of Cd and Se gradually decreases outward from the core center. Also provided is a method for preparing the core-shell type light-emitting quantum dot. By having the alloy core, the first shell layer with a zinc blende structure, and the second shell layer with a wurtzite structure, the core-shell type quantum dot can achieve quantum efficiency of more than 95% and have high-temperature resistance and excellent water- and oxygen-barrier performance.

Abstract: Disclosed are devices and methods for analyzing an analyte, such as white blood cells in liquid samples.

Abstract: The present disclosure discloses a memory access interface device. A data processing circuit receives a data signal including 2M pieces of data from a memory device. A sampling clock generation circuit receives a data strobe signal from the memory device to generate a valid data strobe signal having P valid strobe pulses and further generate a sampling clock signal accordingly, in which P is larger than M. A sampling circuit samples the data signal according to the sampling clock signal to generate sampling results. A control circuit determines valid sampling results according to a time difference between the valid data strobe signal and the data signal and outputs valid data generated according to the valid sampling results as a read data signal to a memory access controller.

Abstract: In a method of inspection of a semiconductor substrate a first beam of light is split into two or more second beams of light. The two or more second beams of light are respectively transmitted onto a first set of two or more first locations on top of the semiconductor substrate. In response to the transmitted two or more second beams of light, two or more reflected beams of light from the first set of two or more first locations are received. The received two or more reflected beams of light are detected to generate two or more detected signals. The two or more detected signals are analyzed to determine whether a defect exists at the set of the two or more first locations.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a heat transfer layer disposed over a substrate, a channel material layer, a gate structure and source and drain terminals. The channel material layer has a first surface and a second surface opposite to the first surface, and the channel material layer is disposed on the heat transfer layer with the first surface in contact with the heat transfer layer. The gate structure is disposed above the channel material layer. The source and drain terminals are in contact with the channel material layer and located at two opposite sides of the gate structure.

Abstract: An embodiment device includes a first source/drain region over a semiconductor substrate and a dummy fin adjacent the first source/drain region. The dummy fin comprising: a first portion comprising a first film and a second portion over the first portion, wherein the second portion comprises: a second film; and a third film. The third film is between the first film and the second film, and the third film is made of a different material than the first film and the second film. A width of the second portion is less than a width of the first portion. The device further comprises a gate stack along sidewalls of the dummy fin.

Abstract: The present disclosure relates to a microfluidic devices and methods for culturing bone marrow cells. Aspects include methods of preparing microfluidic devices and culturing bone marrow cells with the microfluidic devices. In some aspects, a method includes providing a microfluidic device having an upper chamber, a lower chamber, and a porous membrane separating the upper chamber from the lower chamber. The method further includes seeding walls of the lower chamber and a bottom surface of the membrane with endothelial cells. The method further includes providing a matrix within the upper chamber. The matrix includes fibrin gel and bone marrow cells. The method further includes filling or perfusing the upper chamber with a media.

Abstract: A layout design methodology is provided for a device that includes two or more identical structures. Each device can have a first die, a second die stacked over the first die and a third die stacked over the second die. The second die can include a first through-silicon via (TSV) and a first circuit, and the third die can include a second TSV and a second circuit. The first TSV and the second TSV can be linearly coextensive. The first and second circuit can each be a logic circuit having a comparator and counter used to generate die identifiers. The counters of respective device die can be connected in series between the dice. Each die can be manufactured using the same masks but retain unique logical identifiers. A given die in a stack of dice can thereby be addressed by a single path in a same die layout.

Abstract: An imaging lens assembly, having an optical axis, includes an imaging lens set and a lens holding member. The lens holding member accommodates the imaging lens set for aligning the imaging lens set with the optical axis. The lens holding member includes a plurality of light-blocking structures, which are disposed on an object side of the imaging lens set and surround the optical axis for forming a light passing hole. Each of the light-blocking structures is a straight-line shape and has two end points and one central point, and the central point is closer to the optical axis than each of the two end points thereto. A maximum radius of the light passing hole is defined by a position near each of the two end points, and a minimum radius thereof is defined by a position near the central point.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.