Patents by Inventor Chou

Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11726291
    Abstract: An imaging lens assembly includes a plastic barrel and a lens set, and the lens set is disposed in the plastic barrel. The plastic barrel includes an object-side outer surface, a first inner surface and a second inner surface. The lens set has an optical axis, and includes, in order from an object side to an image side thereof, at least one plastic lens element and a spacer. A light-absorbing coating is disposed on the plastic lens element. The spacer includes an object-side connecting surface and a relative surface. When the object-side connecting surface is connected with a neighboring object-side optical element, the relative surface is out of touch with the neighboring object-side optical element. There is an overlap between the second inner surface and the relative surface along a direction parallel to the optical axis.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: August 15, 2023
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Cheng-Feng Lin, Ming-Ta Chou
  • Patent number: 11728364
    Abstract: A method includes forming image sensors in a semiconductor substrate, thinning the semiconductor substrate from a backside of the semiconductor substrate, forming a dielectric layer on the backside of the semiconductor substrate, and forming a polymer grid on the backside of the semiconductor substrate. The polymer grid has a first refractivity value. The method further includes forming color filters in the polymer grid, wherein the color filters has a second refractivity value higher than the first refractivity value, and forming micro-lenses on the color filters.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kun-Huei Lin, Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Cheng Yuan Wang
  • Patent number: 11729780
    Abstract: A method performed by a BS for configuring CSI reporting is provided. The method includes transmitting a CSI reporting configuration to a UE on a first BWP; transmitting a first BWP switch indication to the UE on the first BWP, the first BWP switch indication being used to request the UE to switch to a second BWP; transmitting a second BWP switch indication to the UE after the UE switches from the first BWP to the second BWP, the second BWP switch indication being used to request the UE to switch back to the first BWP; and receiving a CSI report from the UE based on the CSI reporting configuration, without providing any CSI reporting activation command to the UE after the UE switches back to the first BWP according to the second BWP switch indication. A BS using the same is also provided.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: August 15, 2023
    Assignee: FG Innovation Company Limited
    Inventors: Chien-Chun Cheng, Chie-Ming Chou, Yu-Hsin Cheng
  • Patent number: 11726290
    Abstract: An imaging lens system has an optical axis and an image surface through which the optical axis passes. The imaging lens system includes a plastic lens barrel surrounding the optical axis. The plastic lens barrel includes an image-side portion and an object-side aperture through which the optical axis passes, and the image-side portion is located between the image surface and the object-side aperture. The image-side portion includes a protrusive structure surrounding the optical axis and extending towards the image surface. The protrusive structure has an inner surface facing the optical axis, an outer surface disposed opposite to the inner surface and located farther away from the optical axis than the inner surface and a reflection-reducing surface extending towards the image surface and connected to and located between the inner surface and the outer surface. The protrusive structure includes a reflection-reducing structure disposed on the reflection-reducing surface.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: August 15, 2023
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Yu Chen Lai, Ming-Ta Chou, Cheng-Feng Lin
  • Publication number: 20230248366
    Abstract: Method of endovascular intervention in neurovascular anatomy of a patient including deploying an anchor of a tethering device in an anchoring vessel of a neurovascular anatomy, the anchor coupled to a tether extending proximally from the anchor. Method includes advancing a guide-sheath over the tether of the tethering device anchored in the anchoring vessel and attached to the tether, the guide-sheath includes at least one lumen and a distal opening from the lumen. Method includes advancing a treatment device through the lumen of the guide-sheath and out the distal opening from the at least one lumen and through an entrance of a target intracranial vessel, and deploying the treatment device at a treatment site within the target intracranial vessel without a combined therapy of two or more anti-platelet therapeutic agents during a pen-procedural period. Related systems, devices, and methods are disclosed.
    Type: Application
    Filed: December 13, 2022
    Publication date: August 10, 2023
    Inventors: TONY M. CHOU, Joey English
  • Publication number: 20230254890
    Abstract: A communication system includes an antenna, a first wireless communication circuit, a second wireless communication circuit, a switching circuit, and a control circuit. During a second mode, a transmission and reception period of the antenna is divided by the control circuit into a plurality of first scheduling periods and a plurality of second scheduling periods interleaved with the first scheduling periods. The control circuit controls the switching circuit to select the first path or the second path to connect the antenna to the first wireless communication circuit or the second wireless communication circuit, according to a second priority sequence and a third priority sequence during the first scheduling periods and the second scheduling periods, respectively. The second priority sequence is different from the third priority sequence.
    Type: Application
    Filed: December 29, 2022
    Publication date: August 10, 2023
    Inventors: Hsin-I CHOU, Yung-Ching HSIEH, Jian-Jun ZHOU
  • Publication number: 20230251499
    Abstract: An imaging lens assembly includes a plastic barrel and an imaging lens set. The plastic barrel includes an object-side aperture and a first annular surface. The imaging lens set includes a plurality of optical elements, wherein at least one of the optical elements is a plastic lens element, and the plastic lens element includes an effective optical portion, a peripheral portion, a second annular surface, and an object-side connecting surface. The peripheral portion is formed around the effective optical portion. The second annular surface is formed on an object-side surface of the plastic lens element and surrounds the effective optical portion. The object-side connecting surface is formed on the object-side surface of the plastic lens element and surrounds the effective optical portion, and the object-side connecting surface is connected with one of the optical elements disposed on an object side of the plastic lens element.
    Type: Application
    Filed: April 19, 2023
    Publication date: August 10, 2023
    Inventors: Hsiang-Chi TANG, Cheng-Chen LIN, Ming-Ta CHOU
  • Publication number: 20230253041
    Abstract: A memory circuit includes a first driver circuit, a memory cell array including a first column of memory cells, a first transistor coupled between the first driver circuit and the memory cell array, a second driver circuit, a first column of tracking cells and a header circuit coupled to the first driver circuit and the second driver circuit. The first transistor is configured to receive a first select signal. The first column of tracking cells is configured to track a leakage current of the first column of memory cells, and is coupled between a first conductive line and a second conductive line, the first conductive line being coupled to the second driver circuit.
    Type: Application
    Filed: April 20, 2023
    Publication date: August 10, 2023
    Inventors: Chin-I SU, Chung-Cheng CHOU, Yu-Der CHIH, Zheng-Jun LIN
  • Publication number: 20230253389
    Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a fan-out package and a memory package stacked on the fan-out package. The fan-out package includes a first redistribution layer (RDL) structure, a first logic die, through via (TV) interconnects, and first conductive structures. The first logic die and the first conductive structures are in contact with the first RDL structure. The TV interconnects are electrically connected to the first RDL structure. The memory package includes a first substrate, a memory die, and second conductive structures. The memory die and the second conductive structures are disposed on the first substrate. The memory die is electrically connected to the first logic die using the TV interconnects and the first RDL structure. The semiconductor package assembly further includes a second substrate electrically connected to the first logic die using the first conductive structures.
    Type: Application
    Filed: December 22, 2022
    Publication date: August 10, 2023
    Inventors: Shih-Yi SYU, Wen-Chou WU
  • Publication number: 20230253497
    Abstract: A high voltage semiconductor device includes a semiconductor substrate, first and second deep well regions, and first and second well regions disposed in the semiconductor substrate. The second deep well region is located above the first deep well region. The first well region is located above the first deep well region. The second well region is located above the second deep well region. A conductivity type of the second deep well region is complementary to that of the first deep well region. A conductivity type of the second well region is complementary to that of the first well region and the second deep well region. A length of the second deep well region is greater than or equal to that of the second well region and less than that of the first deep well region. The first well region is connected with the first deep well region.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ling-Chun Chou, Te-Chi Yen, Yu-Hung Chang, Kun-Hsien Lee, Kai-Lin Lee
  • Publication number: 20230249225
    Abstract: A chemical mechanical polishing system includes a platen to support a polishing pad, a boiler, a component that is movable between a first position spaced from the polishing pad and a second position in contact with the polishing pad, a plurality of nozzles to direct steam from the boiler onto the component of the polishing system when located at the first position, an actuator to move the component from the first position to the second position in contact with the polishing pad, and a controller configured to cause the treatment station to direct the steam onto the component to clean the component, and cause the actuator to move the cleaned component from the treatment station into contact with the polishing pad.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Inventors: Haosheng Wu, Jianshe Tang, Hari Soundararajan, Shou-Sung Chang, Hui Chen, Chih Chung Chou, Alexander John Fisher, Paul D. Butterfield
  • Publication number: 20230255020
    Abstract: A semiconductor structure includes a substrate and a buried gate structure in the substrate. The buried gate structure includes a gate dielectric layer formed on the sidewall and the bottom surface of a trench in the substrate, a barrier layer formed in the trench and on the sidewall and the bottom surface of the gate dielectric layer, a first work function layer formed in the trench and including a main portion and a protruding portion, a second work function layer formed at opposite sides of the protruding portion, and an insulating layer formed in the trench and on the protruding portion of the first work function layer and the second work function layer. The barrier layer surrounds the main portion of the first work function layer. The area of the top surface of the protruding portion is less than the area of the bottom surface of the protruding portion.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Inventors: Te-Hsuan PENG, Kai JEN, Mei-Yuan CHOU
  • Publication number: 20230251140
    Abstract: The present disclosure provides a microbolometer including a substrate, a readout circuit layer disposed above the substrate, a first vanadium oxide layer disposed above the readout circuit layer, a second vanadium oxide layer disposed on the first vanadium oxide layer, and an infrared absorbing layer disposed above the second vanadium oxide layer, in which an oxygen content of the second vanadium oxide is higher than that of the first vanadium oxide layer.
    Type: Application
    Filed: March 18, 2022
    Publication date: August 10, 2023
    Inventor: Chun-Yuan CHOU
  • Publication number: 20230253243
    Abstract: A method includes forming a first dielectric layer over a source/drain region, and forming a source/drain contact plug over and electrically connecting to the source/drain region. A top portion of the source/drain contact plug has a first lateral dimension. An implantation process is performed to implant a dopant into the first dielectric layer. The implantation process results in the source/drain contact plug to have a second lateral dimension smaller than the first lateral dimension. The method further includes forming a second dielectric layer over the etch stop layer, and forming a gate contact plug adjacent to the source/drain contact plug.
    Type: Application
    Filed: March 27, 2023
    Publication date: August 10, 2023
    Inventors: Kuo-Ju Chen, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Meng-Han Chou
  • Publication number: 20230251936
    Abstract: A data protection method for protecting backup data stored in a data backup device is executed by a mobile device. When the mobile device is included in a trust circle of the data backup device, the mobile device can receive a certified signal, can execute a file manager of a backup APP for loading the backup data, and can generate a first invitation code. Otherwise, the mobile device cannot access the backup data, and displays a code input menu for inputting a second invitation code. The data backup device can certify the first invitation code and the second invitation code for determining whether the mobile device can be added into the trust circle of the data backup device. Therefore, the mobile device included in the trust circle can access the backup data, and the privacy of the backup data can be secured.
    Type: Application
    Filed: February 10, 2022
    Publication date: August 10, 2023
    Inventors: CALVINSON CHANG, STANLEY CHU, CHIHHAN CHOU
  • Publication number: 20230253308
    Abstract: A method for manufacturing a semiconductor device includes forming a conductive feature in a first dielectric layer; forming a second dielectric layer on the first dielectric layer; forming a trench that penetrates through the second dielectric layer, and terminates at the conductive feature; forming a contact layer in the trench and on the conductive feature; etching back the contact layer to form a first via contact feature in the trench, the first via contact feature being electrically connected to the conductive feature; and forming a second via contact feature on the first via contact feature in the trench.
    Type: Application
    Filed: February 10, 2022
    Publication date: August 10, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hung CHU, Po-Chin CHANG, Tzu-Pei CHEN, Yuting CHENG, Kan-Ju LIN, Chih-Shiun CHOU, Hung-Yi HUANG, Pinyen LIN, Sung-Li WANG, Sheng-Tsung WANG, Lin-Yu HUANG, Shao-An WANG, Harry CHIEN
  • Publication number: 20230253284
    Abstract: The present disclosure describes heat dissipation structures formed in functional or non- functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.
    Type: Application
    Filed: April 19, 2023
    Publication date: August 10, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei CHENG, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
  • Publication number: 20230254510
    Abstract: A video encoding system in which pixel data is decomposed into frequency bands prior to encoding. The frequency bands are organized into blocks that are provided to a block-based encoder. The encoded frequency data is packetized and transmitted to a receiving device. On the receiving device, the encoded data is decoded to recover the frequency bands. Wavelet synthesis is then performed on the frequency bands to reconstruct the pixel data for display. The system may encode parts of frames (tiles or slices) using one or more encoders and transmit the encoded parts as they are ready. A pre-filter component may perform a lens warp on the pixel data prior to the wavelet transform.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Applicant: Apple Inc.
    Inventors: Jim C. Chou, Sorin C. Cismas
  • Patent number: 11721882
    Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: August 8, 2023
    Assignee: MediaTek Inc.
    Inventors: Fu-Yi Han, Che-Ya Chou, Che-Hung Kuo, Wen-Chou Wu, Nan-Cheng Chen, Min-Chen Lin, Hsing-Chih Liu
  • Patent number: 11722357
    Abstract: Embodiments of a Network Manager (NM), a (NFVO), and methods of communication are disclosed herein. The NM may transfer, to the NFVO, an update NS request message to update the NS instance based on the new NSD. The NM may encode the update NS request message to include: an nsInstanceID parameter that identifies the NS instance, and an updateType parameter that indicates a type of update for the NS instance. One value of “AssocPnfWithPnfProfile” for the updateType parameter may indicate a request to associate the PNF of the NS instance with a new or updated PNF profile indicated by the new NSD. Another value of “AssocVnfWithVnfProfile” for the updateType parameter may indicate a request to associate the VNF of the NS instance with a new or updated VNF profile indicated by the new NSD.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: August 8, 2023
    Assignee: Apple Inc.
    Inventors: Joey Chou, Yizhi Yao