Abstract: A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Abstract: A fabric having a restraining function is fabricated through at least one yarn having thermoplastic fibers, at least one surface of the fabric has hairiness formed with a plurality of thermoplastic hairs, wherein a first restraining hair having a distal end formed with a spherical member and/or a columnar member is formed through at least a part of the thermoplastic hairs, second restraining hair having a distal end formed with an irregular deformed member is formed through at least a part of the first restraining hairs, so that the at least one surface of the fabric is able to provide a restraining function in a horizontal direction and in a vertical direction to a plurality of fibriform loops.

Abstract: A semiconductor structure includes: a semiconductor substrate; a first source/drain feature and a second source/drain feature over the semiconductor substrate; and semiconductor layers extending longitudinally in a first direction and connecting the first source/drain feature and the second source/drain feature. The semiconductor layers are spaced apart from each other in a second direction perpendicular to the first direction. The semiconductor structure further includes inner spacers each between two adjacent semiconductor layers; metal oxide layers interposing between the inner spacers and the semiconductor layers; and a gate structure wrapping around the semiconductor layers and the metal oxide layers.

Abstract: A method of forming semiconductor device includes forming an active layer in a substrate including forming components of one or more transistors; forming an MD and gate (MDG) layer over the active layer including forming a gate line; forming a metal-to-S/D (MD) contact structure; and forming a waveguide between the gate line and the MD contact structure; forming a first interconnection layer over the MDG layer including forming a first via contact structure over the gate line; forming a second via contact structure over the MD contact structure; and forming a heater between the first and second via contact structures and over the waveguide.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a fin disposed in a first region of the semiconductor device, channel members disposed in a second region of the semiconductor device and stacked in a vertical direction, first and second metal gates disposed on a top surface of the fin, a third metal gate wrapping around each of the channel members, a first implant region in the fin with a first conductivity type, and a second implant region in the fin with a second conductivity opposite the first conductivity type. The fin includes first and second type epitaxial layers alternatingly disposed in the vertical direction. The first and second type epitaxial layers have different material compositions. The first type epitaxial layers and the channel members have the same material composition.

Abstract: A method and apparatus for intensifying current leakage between adjacent memory cells includes that: a write operation is performed on a memory array, to form a column strip test pattern, the column strip test pattern being formed by arranging low-level memory cells and high-level memory cells in columns, and N columns of high-level memory cells being present between two adjacent columns of low-level memory cells, N?2; and voltage adjustment is performed on the low-level memory cells and the high-level memory cells, to increase potential differences between the low-level memory cells and the high-level memory cells.

Abstract: A solution for deteriorated non-volatile memory is shown. When a controller determines that raw data read from the non-volatile memory is undesirable data, the controller performs safety moving of valid data of an erasure unit that contains the raw data to safely move the valid data of the erasure unit, wherein the erasure unit is a high-risk block, and the raw data in the non-volatile memory is regarded as being in a deteriorated physical address. Prior to being moved in the safety moving, the raw data is changed so that it is different from the undesirable data. In an exemplary embodiment, the undesirable data is all-1's data or all-0's data.

Abstract: A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.

Abstract: The invention provides a radio frequency (RF) module and associated method with envelope tracking (ET) power supply in a device. The RF module may comprise a plurality of transmitters, an ET output, and an ET multiplexer. Each said transmitter may comprise an ET port and one or more RF outputs, and may be configured for providing an RF signal to one of said one or more RF outputs, and providing an ET signal, which reflects an envelope of the RF signal, to the ET port. The ET multiplexer may be coupled between said ET ports of the plurality of transmitters and the ET output, for selectively relaying one of said ET ports to the ET output.

Abstract: Some implementations described herein provide techniques and apparatuses for a semiconductor processing tool including an electrostatic chuck having a voltage-regulation system to regulate an electrical potential throughout regions of a semiconductor substrate positioned above the electrostatic chuck. The voltage-regulation system may determine that an electrical potential within a region of the semiconductor substrate does not satisfy a threshold. The voltage-regulation system may, based on determining that the electrical potential throughout the region does not satisfy the threshold, position one or more electrically-conductive pins within the region. While positioned within the region, the one or more electrically-conductive pins may change the electrical potential of the region.

Abstract: A semiconductor device includes a plurality of semiconductor fins, at least one gate stack, a refill isolation, and an air gap. Each of the semiconductor fins extends in an X direction. Two adjacent ones of the semiconductor fins are spaced apart from each other in a Y direction transverse to the X direction. The at least one gate stack has two stack sections spaced apart from each other in the Y direction. The stack sections are disposed over two adjacent ones of the semiconductor fins, respectively. The refill isolation and the air gap are disposed between the stack sections.

Abstract: A solution for deteriorated non-volatile memory is shown. When determining that raw data read from the non-volatile memory is undesirable data, the controller updates a deterioration table to record a deteriorated logical address of the raw data that is the undesirable data. When performing garbage collection from a source block associated with the deteriorated logical address to a destination block and determining that the deteriorated logical address is listed in the deterioration table, the controller invalidates target data stored in the source block and mapped to the deteriorated logical address, without moving the target data from the source block to the destination block in the garbage collection.

Abstract: A display driver circuit for controlling a display panel having a plurality of light-emission diode (LED) strings includes a plurality of current regulators and a control circuit. Each of the plurality of current regulators is configured to control one of the plurality of LED strings. The control circuit, coupled to the plurality of current regulators, is configured to generate a plurality of pulses in a plurality of pulse width modulation (PWM) signals and output each of the plurality of PWM signals to a respective current regulator among the plurality of current regulators. Wherein, the plurality of pulses are scrambled.

Abstract: A preclean process may be omitted from a eutectic bonding sequence. To remove oxide from one or more surfaces of a device wafer of a micro-electromechanical-system (MEMS) structure, a duration of an acid-based etch process in the eutectic bonding sequence may be increased relative to the duration of the acid-based etch process when the preclean process is performed. The increased duration of the acid-based etch process enables the acid-based etch process to remove the oxide from the one or more surfaces of the device wafer without the use of a preceding preclean process. This reduces the complexity and cycle time of the eutectic bonding sequence, reduces the risk of stiction between suspended mechanical components of the MEMS structure, and/or reduces the likelihood that the MEMS structure may be rendered defective or inoperable during manufacturing, which increases process yield.

Abstract: The present disclosure generally relates to compounds class I HDAC inhibitors, their production and applications. The compounds possess epigenetic immunomodulatory activities in the tumor microenvironment (TME) and thus inhibit growth of tumor cells.

Abstract: A solution for deteriorated non-volatile memory is shown. When determining that raw data read from the non-volatile memory is undesirable data, the controller updates a deterioration table to record a deteriorated logical address of the raw data that is the undesirable data. In response to a read request that a host issues to read the non-volatile memory for data of the deteriorated logical address, the controller obtains the deteriorated logical address from the deterioration table and informs the host that deterioration has happened at the deteriorated logical address.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate; a gate electrode disposed within the substrate; a gate dielectric layer disposed within the substrate and surrounding the gate electrode; a plurality of first protection structures disposed over the gate electrode; a second protection structure disposed over the gate dielectric layer and contacting the gate dielectric layer; and a pair of source/drain regions on opposing sides of the gate dielectric layer.

Abstract: Systems and methods are described for removing an embolus in a cerebral vessel of a patient. The assembled system of devices includes a catheter having a catheter lumen and a distal end and a catheter advancement element extending through the catheter lumen. A tapered distal end region of the catheter advancement element extends distal to the distal end of the catheter. The assembled system of devices is advanced together towards an occlusion site in a cerebral vessel of a patient visible on angiogram. The occlusion site includes an angiographic limit of contrast and an embolus downstream of the angiographic limit of contrast. The catheter advancement element is advanced to a location past the angiographic limit of contrast without crossing the embolus. The catheter is advanced to position the distal end of the catheter at a treatment site located past the angiographic limit of contrast and aspiration applied.

Abstract: An information handling system locks to a display stand and/or an external object with a locking mount coupled to the display stand having a Kensington lock and a padlock. The locking mount has a lock switch with an unlocked position to accept and release the information handling system securing members and a lock position that engages the securing members with a lock plate to prevent removal of the information handling system. In the unlocked position, the Kensington lock and padlock loop are unavailable for securing the information handling system. In the locked position, the Kensington lock slot is unblocked to accept a securing cable and the padlock loop will extend from a retract position to accept a padlock. When a cable fits in the slot and/or a padlock fits in the padlock loop, the lock switch is engaged in the locked position to prevent removal of the information handling system securing members.

Abstract: One wireless communication device includes a transmitter circuit and a control circuit, wherein the control circuit sets a request to send (RTS) frame, and controls the transmitter circuit to transmit the RTS frame via at least one channel excluding a preamble punctured channel. Another wireless communication device includes a transmitter circuit and a control circuit, wherein the control circuit sets an RTS frame, and controls the transmitter circuit to transmit the RTS frame via a plurality of channels including the preamble punctured channel.