Abstract: A processing-in-memory (PIM) device may include a plurality of memory banks configured to provide plural groups of weight data, a global buffer configured to provide plural sets of vector data, and a plurality of multiplication/accumulation (MAC) operators configured to perform MAC operations of the plural groups of weigh data and the plural sets of vector data. Each of the plurality of MAC operators includes a plurality of multiple operation circuits. Each of the plurality of multiple operation circuits is configured to perform an arithmetic operation in a first operation mode, a second operation mode, or a third operation mode according to first to third selection signals.

Abstract: A semiconductor system includes a controller outputting a chip selection signal and a command address for performing a read operation and then outputting the chip selection signal and the command address for performing an ECS operation, and a semiconductor device including a plurality of memory cells and generating a latch row address and a latch column address by latching the command address when an error occurs in internal data that are output from a memory cell that is selected, among a plurality of memory cells, after the start of the read operation based on the chip selection signal and the command address, determining the priority of the ECS operation for the plurality of memory cells based on the latch row address and the latch column address, and storing the internal data in the same memory cell again by correcting the error of the internal data.

Abstract: A semiconductor system includes a controller configured to output a command and address for performing an ECS operation after the start of entry into a power-down operation, receive data and output the data in response to correcting one or more errors occurring in the data, and output a command for performing a self-refresh operation when the ECS operation is terminated, and a semiconductor device configured to output, as the data, internal data stored in multiple memory cells after the start of a read operation of the ECS operation in response to receiving the command and address, receive the data having the one or more errors corrected after the start of a write operation of the ECS operation, store the data having the one or more errors corrected, and perform a self-refresh operation on the multiple memory cells after receiving the command when the ECS operation is terminated.

Abstract: A processing-in-memory (PIM) device includes a first memory region, a second memory region, a third memory region, and a multiplication-and-accumulation MAC circuit. The first memory region is configured to store weight data comprised of elements of a weight matrix. The second memory region is configured to store vector data comprised of elements of a vector matrix. The third memory region is configured to store constant data. The MAC circuit is configured to selectively perform a MAC arithmetic operation of the weight data and the vector data or an element-wise multiplication (EWM) arithmetic operation of the weight data and the constant data.

Abstract: A semiconductor device includes a self-test circuit configured to generate an internal clock having a higher frequency than a clock applied from a device external to the semiconductor device, to generate an instruction signal from a pre-instruction signal extracted through a data line, and to generate an internal control signal from the instruction signal. The semiconductor device also includes a command control circuit configured to generate a test command to perform a self-test for determining whether a defect has occurred in first memory cells and second memory cells based on the internal clock and the internal control signal. The semiconductor device further includes a data control circuit configured to output data stored in the first memory cells based on the test command, and to store data output from the first memory cells in the second memory cells.

Abstract: A multiplication-and-accumulation (MAC) circuit includes a MAC operator and a data input circuit. The MAC operator selectively performs a MAC arithmetic operation of weight data and vector data or an element-wise multiplication (EWM) arithmetic operation of the weight data and constant data. The data input circuit provides the MAC operator with the weight data and the vector data when the MAC operator performs the MAC arithmetic operation and provides the MAC operator with the weight data and the constant data when the MAC operator performs the EWM arithmetic operation.

Abstract: An arithmetic device includes an activation function (AF) control circuit, a data storage circuit, and an output distribution signal generation circuit. The AF control circuit generates a column address, a data selection signal, and an internal control signal based on an arithmetic result signal during an activation operation. The data storage circuit outputs activation data from a memory cell array that is selected by the column address and a row address. The output distribution signal generation circuit generates an output distribution signal from the activation data based on the data selection signal and the internal control signal.

Abstract: A processing-in-memory (PIM) device includes memory banks, first and second global buffers, multiplying-and-accumulating (MAC) operators, and output circuits. Each memory bank includes a left memory bank providing left weigh data and a right memory bank providing right weigh data. The first global buffer provides left vector data, and the second global buffer provides right vector data. Each MAC operator includes a left MAC operator performing a MAC operation on the left weight data and the left vector data to generate left MAC data and a right MAC operator performing a MAC operation on the right weight data and the right vector data to generate right MAC data. Each output circuit adds the left MAC data to the right MAC data to generate MAC result data and outputs the MAC result data or activation function-processed MAC result data in response to first and second MAC read signals.

Abstract: A processing-in-memory device includes a data storage region and an arithmetic circuit. The data storage region includes a first memory bank in which first data is divided into a first portion and a second portion and stored, and a second memory bank in which second data is divided into a first portion and a second portion and stored. The arithmetic circuit performs multiplication/accumulation operations on the first data and the second data and outputs final MAC result data.

Abstract: An arithmetic device includes a multiplying-accumulating (MAC) operator and an activation function (AF) circuit. The MAC operator performs a MAC arithmetic operation for weight data and vector data to generate an arithmetic result signal. The AF circuit stores a look-up table for an activation function, adjusts a number of logic level combinations of an input distribution signal that correspond to each logic level combination of the output distribution signal, among a plurality of logic level combinations of the output distribution signal, based on an input range of the activation function. The AF circuit selects and outputs the output distribution signal that corresponds to the input distribution signal based on the look-up table. The input range of the activation function is based on a relative number of errors that occur.

Abstract: An operation method of a buffer chip may include receiving first control signals for setting a first memory chip; buffering the first control signals and transmitting the buffered signals to the first memory chip; storing a setting value of the first memory chip in response to the first control signals; receiving second control signals for setting a second memory chip; buffering the second control signals and transmitting the buffered second control signals to the second memory chip; storing a setting value of the second memory chip in response to the second control signals; receiving third control signals for applying the setting value of the first memory chip; buffering the third control signals and transmitting the buffered third control signals to the first memory chip; and applying the stored setting value of the first memory chip as a setting value of a buffer chip in response to the third control signals.

Abstract: An electronic system includes a control system configured to transmit an encrypted bit stream, an electronic device configured to extract a security key by decrypting the encrypted bit stream and to compare the security key with a check security key to extract programming data for a programming operation by decrypting the encrypted bit stream when the security key and the check security key are the same as each other.

Abstract: A processing-in-memory (PIM) device includes a first memory region, a second memory region, a third memory region, and a multiplication-and-accumulation MAC circuit. The first memory region is configured to store weight data comprised of elements of a weight matrix. The second memory region is configured to store vector data comprised of elements of a vector matrix. The third memory region is configured to store constant data. The MAC circuit is configured to selectively perform a MAC arithmetic operation of the weight data and the vector data or an element-wise multiplication (EWM) arithmetic operation of the weight data and the constant data.

Abstract: A memory module includes a clock driver configured to receive an external clock through a module pin and configured to generate an internal clock that is transmitted to memory chips by delaying a division clock that is generated from the external clock by a clock delay interval. The clock driver adjusts the clock delay interval by comparing the phase of the division clock and the phase of a feedback division clock that is generated from the internal clock.

Abstract: A processing-in-memory (PIM) device includes a data register configured to store reference value data, and a multiplication/accumulation (MAC) operator configured to perform a comparison operation, a multiplication operation, and an addition operation on first data and second data, based on the reference value data to generate MAC operation result data when a MAC operation is performed.

Abstract: A memory controller includes a scheduler configured to generate an active command and an active address, and determine whether to issue the active command and the active address according to an output control signal; a row-hammer detector configured to generate the output control signal by checking a row-hammer possibility based on the active command and the active address; and a memory interface configured to provide the active command and the active address issued by the scheduler to a memory device.

Abstract: A semiconductor device includes a memory circuit including first and second banks and configured to count the numbers of inputs of first and second active signals for executing active operations on the first and second banks to generate a counting signal and to generate first and second hammering detection signals when the numbers of inputs of the first and second active signals are equal to or greater than a set number, and an active control circuit configured to store an active address as a target address when at least one of the first and second hammering detection signals is enabled, and to execute addition and subtraction operations on the target address to output a result of the addition and subtraction operations as an internal address for at least one of the first and second banks for executing a smart refresh operation, based on the counting signal in a refresh operation.

Abstract: A semiconductor system including: an operation period adjusting circuit configured to generate operation information for adjusting an operation period, when an input count of an active command during a test mode period is equal to or more than a preset count; and a command generation circuit configured to adjust the input count of the active command applied to a semiconductor device during a preset period, by adjusting the operation period on the basis of the operation information.

Abstract: A semiconductor system including: an operation period adjusting circuit configured to generate operation information for adjusting an operation period, when an input count of an active command during a test mode period is equal to or more than a preset count; and a command generation circuit configured to adjust the input count of the active command applied to a semiconductor device during a preset period, by adjusting the operation period on the basis of the operation information.

Abstract: A semiconductor system including: an operation period adjusting circuit configured to generate operation information for adjusting an operation period, when an input count of an active command during a test mode period is equal to or more than a preset count; and a command generation circuit configured to adjust the input count of the active command applied to a semiconductor device during a preset period, by adjusting the operation period on the basis of the operation information.