Patents by Inventor Choung Ki Song

Choung Ki Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210223996
    Abstract: A processing-in-memory device includes a data storage region and an arithmetic circuit. The data storage region includes a first memory bank in which first data is divided into a first portion and a second portion and stored, and a second memory bank in which second data is divided into a first portion and a second portion and stored. The arithmetic circuit performs multiplication/accumulation operations on the first data and the second data and outputs final MAC result data.
    Type: Application
    Filed: January 11, 2021
    Publication date: July 22, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210224038
    Abstract: A processing-in-memory (PIM) device includes a plurality of storage regions, a global buffer, and a plurality of multiplication/accumulation (MAC) circuits. The plurality of MAC circuits are configured to perform a MAC operation of first data from the plurality of storage regions and second data from the global buffer. Each of the plurality of MAC circuits is categorized as either an active MAC circuit or an inactive MAC circuit. The MAC operation includes a selective MAC operation which is selectively performed by the active MAC circuit.
    Type: Application
    Filed: January 15, 2021
    Publication date: July 22, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210224039
    Abstract: A multiplying-and-accumulating (MAC) operator for performing a MAC arithmetic operation of a weight matrix employing “M×N”-number of weight sub-matrixes as elements and a vector matrix employing “N”-number of vector sub-matrixes as elements (where “M” and “N” are natural numbers which are equal to or greater than two). The “M×N”-number of weight sub-matrixes are located at cross points of first to Mth weight matrix group rows and first to Nth weight matrix group columns, respectively. The “N”-number of vector sub-matrixes are located at cross points of first to Nth vector matrix group rows and one vector matrix group column, respectively. The MAC operator is configured to perform the MAC arithmetic operations of a matrix group column unit for the “M”-number of weight sub-matrixes arrayed in each of the first to Nth weight matrix group columns and the vector sub-matrix arrayed in each of the Nth vector matrix group rows.
    Type: Application
    Filed: April 8, 2021
    Publication date: July 22, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210208884
    Abstract: A MAC operator includes a plurality of data type converters and a plurality of multipliers. Each of the plurality of data type converters may receive 16-bit input data of one of first to fourth data types of a floating-point format to convert into L-bit output data of the floating-point format. Each of the plurality of multipliers may perform a multiplication on the “L”-bit output data of the floating-point format outputted from two of the plurality of data type converters to output multiplication result data of the floating-point format.
    Type: Application
    Filed: March 1, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210208878
    Abstract: A processing-in-memory (PIM) device includes a data storage region and an arithmetic circuit. The data storage region is configured to store first data and second data. The arithmetic circuit includes a multiplier for performing a multiplying calculation of the first data and the second data. The arithmetic circuit is configured to perform a multiplication/accumulation (MAC) arithmetic operation of the first data and the second data. The arithmetic circuit includes a zero-detection circuit configured to disable input of the multiplier and to output zero data including multiple bits having a value of ‘0’ as output data of the multiplier, when all bits included in at least one of the first data and the second data have a value of ‘0’.
    Type: Application
    Filed: January 11, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventors: Mun Gyu SON, Choung Ki SONG
  • Publication number: 20210209455
    Abstract: A processing-in-memory (PIM) device includes a plurality of multiplication/accumulation (MAC) operators and a plurality of memory banks. The MAC operators are included in each of a plurality of channels. Each of the plurality of MAC operators performs a MAC arithmetic operation using weight data of a weight matrix. The memory banks are included in each of the plurality of channels and are configured to transmit the weight data of the weight matrix to the plurality of MAC operators. The weight data arrayed in one row of the weight matrix are stored into one row of each of the plurality of memory banks.
    Type: Application
    Filed: January 4, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210209022
    Abstract: A PIM device includes a plurality of first storage regions, a second storage region, and a column control circuit. The second storage region is coupled to each of the plurality of first storage regions through a data transmission line. The column control circuit generates a memory read control signal for reading data stored in an initially selected storage region of the plurality of first storage regions and a buffer write control signal for writing the data read from the initially selected storage region to the second storage region. The column control circuit generates a global buffer read control signal for reading the data written to the second storage region and a memory write control signal for writing the data read from the second storage region to a subsequently selected storage region of the plurality of first storage regions.
    Type: Application
    Filed: December 30, 2020
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210208816
    Abstract: A processing-in-memory (PIM) device includes a first group of storage regions, a second group of storage regions, and a plurality of multiplication/accumulation (MAC) operators. The MAC operators are configured to communicate with the first and second groups of storage regions through a global data input/output (GIO) line. A first storage region corresponding to a storage region of the first group of storage regions, a second storage region corresponding to a storage region of the second group of storage regions, and a first MAC operator corresponding to a MAC operator of the plurality of MAC operators constitute a MAC unit. The first MAC operator is configured to receive first data and second data from the first and second storage regions, respectively, through the GIO line to perform a MAC arithmetic operation of the first and second data and to output a result of the MAC arithmetic operation.
    Type: Application
    Filed: November 5, 2020
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210208881
    Abstract: A neural network system includes a data type converter and a MAC operator. The data type converter may convert 32-bit floating-point format into one of a plurality of 16-bit floating-point formats. The MAC operator may perform MAC operations using 16-bit floating-point format data converted by the data type converter. The MAC operator includes a data type modulator configured to modulate the bit number of the converted 16-bit floating-point format to provide a modulated floating-point format with bit number different from the bit number of the converted 16-bit floating-point format.
    Type: Application
    Filed: February 12, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210208882
    Abstract: A MAC operator includes a plurality of multipliers, a plurality of floating-point to fixed-point converters, an adder tree, an accumulator, and a fixed-point to floating-point converter. Each of the plurality of multipliers may perform a multiplication operation on first data and second data of a single-precision floating-point (FP32) format to output multiplication result data of the FP 32 format. Each of the plurality of floating-point to fixed-point converters may convert the FP 32 format into a fixed-point format. The adder tree may perform a first addition operation on the data of the fixed-point format. The accumulator may perform an accumulation operation on the data output from the adder tree. And the fixed-point to floating-point converter may convert the data of the fixed-point format into data of the FP32 format.
    Type: Application
    Filed: February 12, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210210125
    Abstract: A processing-in-memory (PIM) system includes a host and a PIM controller. The host is configured to generate a request for a memory access operation or a multiplication/accumulation (MAC) operation of a PIM device and also to generate a mode definition signal defining an operation mode of the PIM device. The PIM controller is configured to generate a command corresponding to the request to control the memory access operation or the MAC operation of the PIM device. When the operation mode of the PIM device is inconsistent with a mode set defined by the mode definition signal, the PIM controller controls the memory access operation or the MAC operation of the PIM device after changing the operation mode of the PIM device.
    Type: Application
    Filed: January 7, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210208877
    Abstract: A processing-in-memory (PIM) device includes a data storage region and a multiplication/accumulation (MAC) operator. The data storage region is configured to store first data and second data. The MAC operator is configured to perform a MAC arithmetic operation of the first data and the second data. The MAC operator includes a MAC circuit configured to perform the MAC arithmetic operation to output MAC result data and a data output unit configured to feedback bias data to the MAC circuit prior to the MAC arithmetic operation.
    Type: Application
    Filed: January 8, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210208894
    Abstract: A PIM device writes elements of a first matrix to a first memory bank, and may writes elements of a second matrix to a second memory bank. The PIM device simultaneously reads elements with the same order among the elements of the first and second matrices by simultaneously accessing the first and second memory banks. An MAC operator generates arithmetic data by performing a calculation on data that is read from the first and second memory banks, and writes the arithmetic data to a third memory bank.
    Type: Application
    Filed: January 14, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210208880
    Abstract: A processing-in-memory (PIM) controller includes a read/arithmetic queue logic circuit, a write queue logic circuit, and a scheduling logic circuit. The read/arithmetic queue logic circuit stores read queues and arithmetic queues, generates an arithmetic mode signal when an arithmetic queue exists in the read/arithmetic queue logic circuit, and outputs the arithmetic queue in response to an arithmetic mode enablement signal. The write queue logic circuit stores write queues, generates an arithmetic write signal when an arithmetic write queue exists in the write queue logic circuit, and outputs the write queue in response to an arithmetic write enablement signal. The scheduling logic circuit transmits the arithmetic mode enablement signal to the read/arithmetic queue logic circuit in response to the arithmetic mode signal and transmits the arithmetic write enablement signal to the write queue logic circuit in response to the arithmetic write signal.
    Type: Application
    Filed: January 13, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210210123
    Abstract: A memory system includes a stacked memory device and a controller. The stacked memory device includes a base die and a plurality of memory dies stacked on the base die. Each of the plurality of memory dies has a plurality of channels, and the base die is configured to function as an interface for transmitting signals and data of the pluralities of channels. The controller controls the stacked memory device such that first and second data move control operations are sequentially performed to transmit moving data from a target channel of the pluralities of channels to a destination channel of the pluralities of channels. The first data move control operation is performed to store the moving data in the target channel into the base die, and the second data move control operation is performed to write the moving data stored in the base die into the destination channel.
    Type: Application
    Filed: January 7, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210208817
    Abstract: A memory system includes a plurality of memory dies respectively having at least one channel, a controller configured to control the plurality of memory dies, and a base die configured for interfacing signal and data transmissions between the plurality of memory dies and the controller. The controller is configured to remap a logical channel address of the most frequently used channel to a physical channel address of a channel having a lowest temperature value to transmit the remapped physical channel address to the base die.
    Type: Application
    Filed: January 13, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventors: Woo Jae SHIN, Choung Ki SONG
  • Publication number: 20210208801
    Abstract: A processing-in-memory (PIM) device includes a plurality of memory banks and a plurality of multiplication/accumulation (MAC) operators. The MAC operators perform MAC arithmetic operations using data output from the plurality of memory banks and input into the MAC operators. A page is allocated to have a first page size in the plurality of memory banks in a memory mode. The page is allocated to have a second page size, which is greater than the first page size, in the plurality of memory banks in a MAC arithmetic mode.
    Type: Application
    Filed: January 11, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210208879
    Abstract: A MAC operator includes a plurality of multipliers configured to perform a multiplication operation on a floating-point format first data and a floating-point format second data to output a floating-point format multiplication result data, a plurality of floating-point-to-fixed-point converters configured to receive the floating-point format multiplication result data from each of the plurality of multipliers and convert into a fixed-point format multiplication result data to be output, and an adder tree configured to perform an addition operation on the fixed-point format multiplication result data that is output from the plurality of floating-point-to-fixed-point converters. If a first mantissa of the first data and a second mantissa of the second data are composed of ‘M’-bit (‘M’ being a natural number), each of the plurality of multipliers is configured to perform the multiplication operation so that the fixed-point format multiplication result data includes a mantissa of 2*(M+1) bits.
    Type: Application
    Filed: January 11, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210208814
    Abstract: A processing-in-memory (PIM) system includes a PIM device and a PIM controller. The PIM device includes a first storage region, a second storage region, and a multiplication/accumulation (MAC) operator configured to receive first data and second data from the first and second storage regions, respectively, to perform a MAC arithmetic operation. The PIM controller controls a memory mode and a MAC mode of the PIM device. The PIM controller is configured to generate and transmit a memory command to the PIM device in the memory mode. In addition, the PIM controller is configured to generate and transmit first to fifth MAC commands to the PIM device in the MAC mode.
    Type: Application
    Filed: September 21, 2020
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210208883
    Abstract: A MAC operator includes a plurality of multipliers, a plurality of floating-point to fixed-point converters, and an adder tree. Each of the plurality of multipliers may perform a multiplication operation on first data and second data of a floating-point format to output multiplication result data. Each of the plurality of floating-point to fixed-point converters may convert the data type of the multiplication result data into a fixed-point format. The adder tree may perform a first addition operation on the multiplication result data of the fixed-point format. Each of the plurality of floating-point to fixed-point converters may skip a ‘+1’ operation for processing a negative number and a ‘+1’ operation for roundup processing in a data type converting process, and output round bits equaling to bit values not added by the skipped ‘+1’ operations in the data type converting process.
    Type: Application
    Filed: February 12, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG