Abstract: A processing-in-memory (PIM) device includes a data storage region and a multiplication/accumulation (MAC) operator. The data storage region is configured to store first data and second data. The MAC operator is configured to perform a MAC arithmetic operation of the first data and the second data. The MAC operator includes a MAC circuit configured to perform the MAC arithmetic operation to output MAC result data and a data output unit configured to feedback bias data to the MAC circuit prior to the MAC arithmetic operation.

Abstract: A semiconductor device includes an operation control signal generation circuit and a neural network circuit. The operation control signal generation circuit generates an arithmetic signal and a core read signal based on a command. The neural network circuit outputs first core data and second core data from a core region based on the core read signal, a cell block selection signal, and a cell selection signal. The neural network circuit also performs an arithmetic operation of the first and second core data based on the arithmetic signal to generate arithmetic result data.

Abstract: A processing-in-memory (PIM) device includes a data storage region and an arithmetic circuit. The data storage region is configured to store first data and second data. The arithmetic circuit includes a multiplier for performing a multiplying calculation of the first data and the second data. The arithmetic circuit is configured to perform a multiplication/accumulation (MAC) arithmetic operation of the first data and the second data. The arithmetic circuit includes a zero-detection circuit configured to disable input of the multiplier and to output zero data including multiple bits having a value of ‘0’ as output data of the multiplier, when all bits included in at least one of the first data and the second data have a value of ‘0’.

Abstract: A processing-in-memory (PIM) device includes a plurality of multiplication/accumulation (MAC) units, each of the MAC units including a memory bank and a MAC operator and performing one operation, among a memory operation and a PIM operation, a command mapping register generating one of a memory operation mode signal and a PIM operation mode signal based on a row address that is mapped to the PIM operation to be performed by the plurality of MAC units, and a command decoder generating a memory control signal for the memory operation and a PIM control signal for the PIM operation, wherein the command decoder is configured to generate the PIM control signal in response to the PIM operation mode signal and configured to transmit the PIM control signal to the plurality of MAC units, and configured to generate the memory control signal in response to the memory operation mode signal and configured to transmit the memory control signal to the plurality of MAC units.

Abstract: A multiplication-accumulation (MAC) includes a multiplication circuit, a pre-processing circuit, and an adder tree. The multiplication circuit performs a multiplication operation on a plurality of weight data and a plurality of vector data each having a floating-point format to output a plurality of multiplication data. The pre-processing circuit performs shifting on mantissa data of the plurality of multiplication data by a difference between first maximum exponent data having a greatest value among the exponent data of the plurality of multiplication data and the remaining exponent data to output a plurality of pre-processed mantissa data. The adder tree adds the plurality of mantissa data to output mantissa addition bits.

Abstract: A multiplication-accumulation (MAC) includes a multiplication circuit, a pre-processing circuit, and an adder tree. The multiplication circuit performs a multiplication operation on a plurality of weight data and a plurality of vector data each having a floating-point format to output a plurality of multiplication data. The pre-processing circuit performs shifting on mantissa data of the plurality of multiplication data by a difference between first maximum exponent data having a greatest value among the exponent data of the plurality of multiplication data and the remaining exponent data to output a plurality of pre-processed mantissa data. The adder tree adds the plurality of mantissa data to output mantissa addition bits.

Abstract: A processing-in-memory (PIM) device includes a first memory region, a second memory region, a third memory region, and a multiplication-and-accumulation MAC circuit. The first memory region is configured to store weight data comprised of elements of a weight matrix. The second memory region is configured to store vector data comprised of elements of a vector matrix. The third memory region is configured to store constant data.

Abstract: A multiplication-and-accumulation (MAC) circuit includes a MAC operator and a data input circuit. The MAC operator selectively performs a MAC arithmetic operation of weight data and vector data or an element-wise multiplication (EWM) arithmetic operation of the weight data and constant data. The data input circuit provides the MAC operator with the weight data and the vector data when the MAC operator performs the MAC arithmetic operation and provides the MAC operator with the weight data and the constant data when the MAC operator performs the EWM arithmetic operation.

Abstract: An arithmetic device includes an auto-command/address generation circuit, a first data storage circuit, and a second data storage circuit. The auto-command/address generation circuit generates an auto-load selection signal that activates an auto-load operation based on a level of a power source voltage. In addition, the auto-command/address generation circuit generates an auto-load command for the auto-load operation. The first data storage circuit outputs look-up table data, to which an activation function is applied, to based on the auto-load command. The second data storage circuit stores the look-up table data, output from the first data storage circuit, based on the auto-load command.

Abstract: A memory system includes a plurality of memory dies respectively having at least one channel, a controller configured to control the plurality of memory dies, and a base die configured for interfacing signal and data transmissions between the plurality of memory dies and the controller. The controller is configured to remap a logical channel address of the most frequently used channel to a physical channel address of a channel having a lowest temperature value to transmit the remapped physical channel address to the base die.

Abstract: A processing-in-memory (PIM) device includes a plurality of memory banks and a plurality of multiplication and accumulation (MAC) operators. The plurality of memory banks include a plurality of even memory banks and a plurality of odd memory banks. The plurality of MAC operators include a first MAC operator configured to be shared by a first even memory bank among the plurality of even memory banks and a first odd memory bank among the plurality of odd memory banks. The first MAC operator is configured to alternately perform an even MAC operation and an odd MAC operation.

Abstract: A semiconductor device includes an error check and scrub (ECS) command generation circuit and an ECS control circuit. The ECS command generation circuit generates an internal refresh command after generating an ECS command based on a refresh command and an idle signal. The ECS control circuit generates an ECS mode signal that is activated during an ECS operation based on the ECS command. The ECS control circuit also generates an ECS active command, an ECS read command, and an ECS write command for performing the ECS operation based on the ECS command.

Abstract: A memory system includes a plurality of memory dies respectively having at least one channel, a controller configured to control the plurality of memory dies, and a base die configured for interfacing signal and data transmissions between the plurality of memory dies and the controller. The controller is configured to remap a logical channel address of the most frequently used channel to a physical channel address of a channel having a lowest temperature value to transmit the remapped physical channel address to the base die.

Abstract: A memory system includes a stacked memory device and a controller. The stacked memory device includes a base die and a plurality of memory dies stacked on the base die. Each of the plurality of memory dies has a plurality of channels, and the base die is configured to function as an interface for transmitting signals and data of the pluralities of channels. The controller controls the stacked memory device such that first and second data move control operations are sequentially performed to transmit moving data from a target channel of the pluralities of channels to a destination channel of the pluralities of channels. The first data move control operation is performed to store the moving data in the target channel into the base die, and the second data move control operation is performed to write the moving data stored in the base die into the destination channel.

Abstract: A semiconductor device includes an error correction circuit and a refresh control circuit. The error correction circuit is configured to detect an error included in internal data, to generate a failure detection signal, and to correct the error of the internal data. The refresh control circuit is configured to store an address signal for selecting the internal data in response to the failure detection signal. In addition, the refresh control circuit is configured to generate a refresh address signal for activating a word line connected to memory cells storing the internal data from the address signal when a refresh signal is inputted to the refresh control circuit by a predetermined number of times.

Abstract: A semiconductor device includes an error check and scrub (ECS) command generation circuit and a period signal generation circuit. The ECS command generation circuit generates an ECS command based on a refresh command. The period signal generation circuit generates a sampling period signal, during a sampling period, based on the ECS command and generates an operation period signal, during an operation period, based on the ECS command. A latch error flag is generated to include information on whether errors exist in codewords during the sampling period, and an ECS operation is performed based on the latch error flag, during the operation period, for memory cells that store an erroneous codeword among the codewords.

Abstract: A processing-in-memory (PIM) device includes first to Lth multiplication/accumulation (MAC) operators, first to Lth memory banks, and a plurality of data input/output (I/O) circuits. The first to Lth MAC operators include first to Lth left MAC operators and first to Lth right MAC operators. The plurality of data I/O circuits include left data I/O circuits and right data I/O circuits. A Uth MAC operator among the first to Lth MAC operators is configured to output one of the first to Mth MAC result data through a Uth left MAC operator among the first to Lth left MAC operators or a Uth right MAC operator among the first to Lth right MAC operators. The PIM device is configured to output the MAC result data outputted through the left MAC operators through the left data I/O circuits, and output the MAC result data outputted through the right MAC operators through the right data I/O circuits.

Abstract: An electronic device includes an error correction circuit configured to detect an error included in internal data, to generate a failure detection signal during a read operation, and to correct the error included in the internal data during a refresh operation, and a core circuit configured to store an address signal for activating a word line in which the internal data including the error is stored through as a failure address signal when the failure detection signal is input to the core circuit, and store the error-corrected internal data in the core circuit through a word line activated by the failure address signal during the refresh operation.

Abstract: A processing-in-memory (PIM) device includes first to Lth multiplication/accumulation (MAC) operators, first to Lth memory banks, first to Lth additional adders, and a plurality of data input/output (I/O) circuits. The first to Lth MAC operators include first to Lth left MAC operators and first to Lth right MAC operators. The first to Lth additional adders are configured to generate and output first to Mth MAC result data. The plurality of data I/O circuits include left data I/O circuits and right data I/O circuits. Each of the first to Lth additional adders is classified as either a left additional adder or a right additional adder. The left additional adders are configured to transmit a first portion of the first to Mth MAC result data to the left data I/O circuits, and the right additional adders are configured to transmit a second portion of the first to Mth MAC result data to the right data I/O circuits.

Abstract: A processing-in-memory (PIM) system includes a plurality of PIM devices, a plurality of PIM controllers configured to control respective ones of the plurality of PIM devices, and an interface coupled between a host and the plurality of PIM controllers. The interface transmits first request data to a target PIM controller corresponding to one of the plurality of PIM controllers for execution of a first request output from the host. The interface transmits second request data to all of the plurality of PIM controllers for execution of a second request output from the host.