Abstract: An electronic device includes an error correction circuit configured to detect an error included in internal data, to generate a failure detection signal during a read operation, and to correct the error included in the internal data during a refresh operation, and a core circuit configured to store an address signal for activating a word line in which the internal data including the error is stored through as a failure address signal when the failure detection signal is input to the core circuit, and store the error-corrected internal data in the core circuit through a word line activated by the failure address signal during the refresh operation.

Abstract: A semiconductor die stack includes a lower semiconductor die and an upper semiconductor die. The upper semiconductor die includes a first upper bonding pad disposed in a first upper bonding pad region; and a second upper bonding pad disposed in a second upper bonding pad region. The lower semiconductor die includes a first lower bonding pad disposed in a first lower bonding pad region; and a second lower bonding pad disposed in a second lower bonding pad region. The second upper bonding pad and the first lower bonding pad are vertically aligned and directly bonded to each other. The second upper bonding pad and the first lower bonding pad are not electrically connected to an upper electrical circuit in the upper semiconductor die, and electrically connected to a lower electrical circuit in the lower semiconductor die.

Abstract: A processing-in-memory (PIM) device includes a plurality of multiplication/accumulation (MAC) operators and a plurality of memory banks. The MAC operators are included in each of a plurality of channels. Each of the plurality of MAC operators performs a MAC arithmetic operation using weight data of a weight matrix. The memory banks are included in each of the plurality of channels and are configured to transmit the weight data of the weight matrix to the plurality of MAC operators. The weight data arrayed in one row of the weight matrix are stored into one row of each of the plurality of memory banks.

Abstract: An arithmetic device includes an AF circuit including a first table storage circuit. The AF circuit stores a table input signal into one variable latch selected based on an input selection signal among variable latches included in the first table storage circuit in a look-up table form when a table set signal is activated. The AF circuit extracts a result value of a first activation function realized by a look-up table based on an input distribution signal to output the extracted result value as a fist table output signal for generating an output distribution signal.

Abstract: A processing-in-memory (PIM) system includes a first and second PIM devices and a host. Each of the first and second PIM devices includes a plurality of multiplying-and-accumulating (MAC) operators and a plurality of memory banks supplying weight data to the plurality of MAC operators. The host controls the first and second PIM devices and includes a data buffer. The first and second PIM devices include a first global buffer and a second global buffer, which supply the vector data to the plurality of MAC operators, respectively. The host reads the vector data out of the first and second PIM devices to store the vector data into the data buffer and writes the vector data stored in the data buffer into the first and second global buffers.

Abstract: A MAC operator includes a plurality of data type converters and a plurality of multipliers. Each of the plurality of data type converters may receive 16-bit input data of one of first to fourth data types of a floating-point format to convert into L-bit output data of the floating-point format. Each of the plurality of multipliers may perform a multiplication on the “L”-bit output data of the floating-point format outputted from two of the plurality of data type converters to output multiplication result data of the floating-point format.

Abstract: A multiplication-accumulation (MAC) includes a multiplication circuit, a pre-processing circuit, and an adder tree. The multiplication circuit performs a multiplication operation on a plurality of weight data and a plurality of vector data each having a floating-point format to output a plurality of multiplication data. The pre-processing circuit performs shifting on mantissa data of the plurality of multiplication data by a difference between first maximum exponent data having a greatest value among the exponent data of the plurality of multiplication data and the remaining exponent data to output a plurality of pre-processed mantissa data. The adder tree adds the plurality of mantissa data to output mantissa addition bits.

Abstract: A memory system includes a memory device and a memory controller. The memory device includes a memory area configured to store data and an input/output (I/O) buffering part configured to store data outputted from the memory area. The memory controller is configured to control read operations of the memory device. The memory device is configured to store data of all columns in a selected row designated by a row address among a plurality of rows in the memory area into the I/O buffering part in response to an external command outputted from the memory controller and is configured to output data of a selected column designated by a column address among the data stored in the I/O buffering part, and the memory controller is configured to perform a scheduling operation for successively executing read request commands having the same row address among a plurality of read request commands for performing read operations of the memory device.

Abstract: A semiconductor device may include: a first substrate; a first high-frequency signal through electrode and a first low-frequency signal through electrode passing through the first substrate; a first high-frequency signal conductive pattern and a first low-frequency signal conductive pattern respectively connected to the first high-frequency signal through electrode and the first low-frequency signal through electrode; and one or more first high-frequency signal connection electrodes and one or more first low-frequency signal connection electrodes respectively connected to the first high-frequency signal conductive pattern and the first low-frequency signal conductive pattern, wherein an area of the first low-frequency signal conductive pattern is larger than an area of the first high-frequency signal conductive pattern.

Abstract: A semiconductor system includes a controller configured to generate a command and an address for performing a row hammering tracking operation and performing a precharge operation on a bank on which a tracking write operation of the row hammering tracking operation has been completed and a semiconductor device including the bank and a row hammering storage circuit, the semiconductor device configured to count an active number of the bank that is stored in the row hammering storage circuit by performing a tracking read operation of the row hammering tracking operation based on the command and the address, then store, in the row hammering circuit, the active number of the bank that is counted by performing the tracking write operation of the row hammering tracking operation, and perform the precharge operation on the bank based on the command.

Abstract: A PIM device writes elements of a first matrix to a first memory bank, and may writes elements of a second matrix to a second memory bank. The PIM device simultaneously reads elements with the same order among the elements of the first and second matrices by simultaneously accessing the first and second memory banks. An MAC operator generates arithmetic data by performing a calculation on data that is read from the first and second memory banks, and writes the arithmetic data to a third memory bank.

Abstract: A processing-in-memory (PIM) device includes a data selection circuit, a multiplying-and-accumulating (MAC) circuit, and an accumulative adding circuit. The data selection circuit generates selection data from input data and zero-point data based on a zero-point selection signal. The MAC circuit performs a MAC arithmetic operation for the selection data to generate MAC result data. The accumulative adding circuit accumulatively adds MAC sign data based on a MAC output latch signal to generate MAC latch data. A sign of the MAC sign data is determined by the zero-point selection signal.

Abstract: An arithmetic device includes an arithmetic circuit configured to perform an arithmetic operation to output arithmetic result data and a data output unit configured to feedback bias data to the arithmetic circuit prior to the arithmetic operation.

Abstract: A processing-in-memory (PIM) device includes a plurality of multiplication/accumulation (MAC) operators and a plurality of memory banks. The MAC operators are included in each of a plurality of channels. Each of the plurality of MAC operators performs a MAC arithmetic operation using weight data of a weight matrix. The memory banks are included in each of the plurality of channels and are configured to transmit the weight data of the weight matrix to the plurality of MAC operators. The weight data arrayed in one row of the weight matrix are stored into one row of each of the plurality of memory banks.

Abstract: A processing-in-memory (PIM) device includes a plurality of multiplication/accumulation (MAC) units, each of the MAC units including a memory bank and a MAC operator and performing one operation, among a memory operation and a PIM operation, a command mapping register generating one of a memory operation mode signal and a PIM operation mode signal based on a row address that is mapped to the PIM operation to be performed by the plurality of MAC units, and a command decoder generating a memory control signal for the memory operation and a PIM control signal for the PIM operation, wherein the command decoder is configured to generate the PIM control signal in response to the PIM operation mode signal and configured to transmit the PIM control signal to the plurality of MAC units, and configured to generate the memory control signal in response to the memory operation mode signal and configured to transmit the memory control signal to the plurality of MAC units.

Abstract: A semiconductor system includes a controller configured to generate a command and an address for performing a row hammering tracking operation and performing a precharge operation on a bank on which a tracking write operation of the row hammering tracking operation has been completed and a semiconductor device including the bank and a row hammering storage circuit, the semiconductor device configured to count an active number of the bank that is stored in the row hammering storage circuit by performing a tracking read operation of the row hammering tracking operation based on the command and the address, then store, in the row hammering circuit, the active number of the bank that is counted by performing the tracking write operation of the row hammering tracking operation, and perform the precharge operation on the bank based on the command.

Abstract: A stacked integrated circuit includes a first chip including a first area and a second area that are disposed to be substantially symmetrical to each other in relation to a first rotating axis. The first area includes a first through via set and a first front pad set that are connected by using a first connection method. The second area includes a second through via set and a second front pad set that are connected by using a second connection method. The first through via set and the second through via set are disposed to be substantially symmetrical to each other in relation to the first rotating axis. The first front pad set and the second front pad set are disposed to be substantially symmetrical to each other in relation to the first rotating axis.

Abstract: A semiconductor device includes a memory circuit including first and second banks and configured to count the numbers of inputs of first and second active signals for executing active operations on the first and second banks to generate a counting signal and to generate first and second hammering detection signals when the numbers of inputs of the first and second active signals are equal to or greater than a set number, and an active control circuit configured to store an active address as a target address when at least one of the first and second hammering detection signals is enabled, and to execute addition and subtraction operations on the target address to output a result of the addition and subtraction operations as an internal address for at least one of the first and second banks for executing a smart refresh operation, based on the counting signal in a refresh operation.

Abstract: A processing-in-memory (PIM) system includes a PIM device and a PIM controller. The PIM device includes a first storage region, a second storage region, and a multiplication/accumulation (MAC) operator configured to receive first data and second data from the first and second storage regions, respectively, to perform a MAC arithmetic operation. The PIM controller controls a memory mode and a MAC mode of the PIM device. The PIM controller is configured to generate and transmit a memory command to the PIM device in the memory mode. In addition, the PIM controller is configured to generate and transmit first to fifth MAC commands to the PIM device in the MAC mode.

Abstract: A processing-in-memory (PIM) system includes a PIM device and a PIM controller. The PIM device includes a first storage region, a second storage region, and a multiplication/accumulation (MAC) operator configured to receive first data and second data from the first and second storage regions, respectively, to perform a MAC arithmetic operation. The PIM controller controls a memory mode and a MAC mode of the PIM device. The PIM controller is configured to generate and transmit a memory command to the PIM device in the memory mode. In addition, the PIM controller is configured to generate and transmit first to fifth MAC commands to the PIM device in the MAC mode.