Patents by Inventor Choung Ki Song

Choung Ki Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210208881
    Abstract: A neural network system includes a data type converter and a MAC operator. The data type converter may convert 32-bit floating-point format into one of a plurality of 16-bit floating-point formats. The MAC operator may perform MAC operations using 16-bit floating-point format data converted by the data type converter. The MAC operator includes a data type modulator configured to modulate the bit number of the converted 16-bit floating-point format to provide a modulated floating-point format with bit number different from the bit number of the converted 16-bit floating-point format.
    Type: Application
    Filed: February 12, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210208814
    Abstract: A processing-in-memory (PIM) system includes a PIM device and a PIM controller. The PIM device includes a first storage region, a second storage region, and a multiplication/accumulation (MAC) operator configured to receive first data and second data from the first and second storage regions, respectively, to perform a MAC arithmetic operation. The PIM controller controls a memory mode and a MAC mode of the PIM device. The PIM controller is configured to generate and transmit a memory command to the PIM device in the memory mode. In addition, the PIM controller is configured to generate and transmit first to fifth MAC commands to the PIM device in the MAC mode.
    Type: Application
    Filed: September 21, 2020
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210208877
    Abstract: A processing-in-memory (PIM) device includes a data storage region and a multiplication/accumulation (MAC) operator. The data storage region is configured to store first data and second data. The MAC operator is configured to perform a MAC arithmetic operation of the first data and the second data. The MAC operator includes a MAC circuit configured to perform the MAC arithmetic operation to output MAC result data and a data output unit configured to feedback bias data to the MAC circuit prior to the MAC arithmetic operation.
    Type: Application
    Filed: January 8, 2021
    Publication date: July 8, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210165583
    Abstract: A Processing-In-Memory (PIM) device includes an error correction code (ECC) logic circuit and an error accumulation detection circuit. The error correction code (ECC) logic circuit configured to detect an erroneous bits included in first data to generate a parity bit, and to detect an error correction capability of the first data to generate an error correction fail signal. The error accumulation detection circuit configured to generate an error accumulation signal counted by a pulse of the error correction fail signal. The error correction capability set to the maximum number of erroneous bits that can be corrected by performing an ECC operation on the first data.
    Type: Application
    Filed: February 12, 2021
    Publication date: June 3, 2021
    Applicant: SK hynix Inc.
    Inventors: Choung Ki SONG, Jeong Jun LEE
  • Publication number: 20210158134
    Abstract: An arithmetic device includes an activation function (AF) control circuit and a data storage circuit. The AF control circuit is configured to generate an activation period signal, an activation active signal, and an activation read signal based on an activation control signal. The data storage circuit includes at least one memory bank that is activated based on a bank active signal that is generated based on the activation active signal. The data storage circuit is configured to output data stored in a memory cell array, which is selected by a row address and a column address, as activation data based on the activation read signal.
    Type: Application
    Filed: February 4, 2021
    Publication date: May 27, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210158852
    Abstract: An arithmetic device includes an auto-command/address generation circuit, a first data storage circuit, and a second data storage circuit. The auto-command/address generation circuit generates an auto-load selection signal that activates an auto-load operation based on a level of a power source voltage. In addition, the auto-command/address generation circuit generates an auto-load command for the auto-load operation. The first data storage circuit outputs look-up table data, to which an activation function is applied, based on the auto-load command. The second data storage circuit stores the look-up table data, output from the first data storage circuit, based on the auto-load command.
    Type: Application
    Filed: February 1, 2021
    Publication date: May 27, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Patent number: 11017840
    Abstract: A semiconductor device includes a row address generation circuit, a first region, and a second region. The row address generation circuit is configured to generate a first row address from an active signal and a first bank address and configured to generate a second row address from the active signal and a second bank address. The first region is activated by the first row address and an internal address. The second region is activated by the second row address and the internal address. One of the first and second bank addresses is selectively generated according to a command/address signal.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: May 25, 2021
    Assignee: SK hynix Inc.
    Inventor: Choung Ki Song
  • Publication number: 20210141687
    Abstract: A semiconductor device includes an error check and scrub (ECS) command generation circuit and a period signal generation circuit. The ECS command generation circuit generates an ECS command based on a refresh command. The period signal generation circuit generates a sampling period signal, during a sampling period, based on the ECS command and generates an operation period signal, during an operation period, based on the ECS command. A latch error flag is generated to include information on whether errors exist in codewords during the sampling period, and an ECS operation is performed based on the latch error flag, during the operation period, for memory cells that store an erroneous codeword among the codewords.
    Type: Application
    Filed: June 23, 2020
    Publication date: May 13, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210141691
    Abstract: A semiconductor device includes an error check and scrub (ECS) command generation circuit and an ECS control circuit. The ECS command generation circuit generates an internal refresh command after generating an ECS command based on a refresh command and an idle signal. The ECS control circuit generates an ECS mode signal that is activated during an ECS operation based on the ECS command. The ECS control circuit also generates an ECS active command, an ECS read command, and an ECS write command for performing the ECS operation based on the ECS command.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 13, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210142860
    Abstract: A semiconductor device includes an error check and scrub (ECS) command generation circuit and an ECS control circuit. The ECS command generation circuit generates an ECS command based on a refresh command. During an ECS operation, the ECS control circuit generates an ECS mode signal that is activated based on the ECS command and generates an ECS active command, an ECS read command, and an ECS write command to continue the ECS operation.
    Type: Application
    Filed: April 10, 2020
    Publication date: May 13, 2021
    Applicant: SK hynix Inc.
    Inventors: Choung Ki SONG, Jung Ho LIM
  • Publication number: 20210132953
    Abstract: An arithmetic device includes an input distribution signal generation circuit, an output distribution signal generation circuit, and an output distribution signal compensation circuit. The input distribution signal generation circuit generates an input distribution signal and a compensation signal based on an arithmetic result signal generated from a result of a multiplying-accumulating (MAC) calculation. The output distribution signal generation circuit applies the input distribution signal to an activation function to generate first and second output distribution signals. The output distribution signal compensation circuit compensates for the first output distribution signal based on the compensation signal, the first output distribution signal, and the second output distribution signal to generate a compensated distribution signal.
    Type: Application
    Filed: July 17, 2020
    Publication date: May 6, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210132911
    Abstract: An arithmetic device includes a function storage circuit and an activation function (AF) circuit. The function storage circuit stores and outputs a function selection signal, a first function information signal, and a second function information signal. The AF circuit generates an activation function result data by applying a slope value and a maximum value to a multiplication/accumulation (MAC) result data in a function setting mode that is activated by the function selection signal. The slope value is set based on the first function information signal, and the maximum value is set based on the second function information signal.
    Type: Application
    Filed: December 17, 2020
    Publication date: May 6, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210134351
    Abstract: A semiconductor device includes a row address generation circuit, a first region, and a second region. The row address generation circuit is configured to generate a first row address from an active signal and a first bank address and configured to generate a second row address from the active signal and a second bank address. The first region is activated by the first row address and an internal address. The second region is activated by the second row address and the internal address. One of the first and second bank addresses is selectively generated according to a command/address signal.
    Type: Application
    Filed: March 23, 2020
    Publication date: May 6, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210134349
    Abstract: An arithmetic device includes an auto-command/address generation circuit, a first data storage circuit, and a second data storage circuit. The auto-command/address generation circuit generates an auto-load selection signal that activates an auto-load operation based on a level of a power source voltage. In addition, the auto-command/address generation circuit generates an auto-load command for the auto-load operation. The first data storage circuit outputs look-up table data, to which an activation function is applied, to based on the auto-load command. The second data storage circuit stores the look-up table data, output from the first data storage circuit, based on the auto-load command.
    Type: Application
    Filed: December 17, 2020
    Publication date: May 6, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210133546
    Abstract: An arithmetic device includes an activation function (AF) control circuit, a data storage circuit, and an output distribution signal generation circuit. The AF control circuit generates a column address, a data selection signal, and an internal control signal based on an arithmetic result signal during an activation operation. The data storage circuit outputs activation data from a memory cell array that is selected by the column address and a row address. The output distribution signal generation circuit generates an output distribution signal from the activation data based on the data selection signal and the internal control signal.
    Type: Application
    Filed: January 7, 2021
    Publication date: May 6, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210133545
    Abstract: An arithmetic device includes an AF circuit including a first table storage circuit. The AF circuit stores a table input signal into one variable latch selected based on an input selection signal among variable latches included in the first table storage circuit in a look-up table form when a table set signal is activated. The AF circuit extracts a result value of a first activation function realized by a look-up table based on an input distribution signal to output the extracted result value as a fist table output signal for generating an output distribution signal.
    Type: Application
    Filed: July 2, 2020
    Publication date: May 6, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210132954
    Abstract: An arithmetic device includes a multiplying-accumulating (MAC) operator and an activation function (AF) circuit. The MAC operator performs a MAC arithmetic operation for weight data and vector data to generate an arithmetic result signal. The AF circuit extracts a first bit group and a second bit group from the arithmetic result signal. In addition, the AF circuit generates an input distribution signal based on the first bit group and the second bit group. Moreover, the AF circuit selects and outputs an output distribution signal that corresponds to the input distribution signal based on an activation function.
    Type: Application
    Filed: October 21, 2020
    Publication date: May 6, 2021
    Applicant: SK hynix Inc.
    Inventor: Choung Ki SONG
  • Publication number: 20210132825
    Abstract: A Processing-In-Memory (PIM) device includes a MAC operator, a first storage region and an error correction code (ECC) logic circuit. The MAC operator performs MAC operation of first data and second data. The first storage region provides the first data to the MAC operator. The error correction code (ECC) logic circuit transmit first encoded data to the first storage region by performing a first ECC encoding operation on the first data. The error correction code (ECC) logic circuit transmit first decoded data generated by performing a first ECC decoding operation of the first encoded data transmitted from the first storage region to the MAC operator. The error correction code (ECC) logic circuit generates an error calculation result signal and transmit the an error calculation result signal to the MAC operator when the number of erroneous bits detected in the first ECC decoding operation exceed an error correction capability.
    Type: Application
    Filed: January 14, 2021
    Publication date: May 6, 2021
    Applicant: SK hynix Inc.
    Inventors: Choung Ki SONG, Jeong Jun LEE
  • Publication number: 20210132910
    Abstract: An arithmetic device includes a multiplying-accumulating (MAC) operator and an activation function (AF) circuit. The MAC operator performs a MAC arithmetic operation for weight data and vector data to generate an arithmetic result signal. The AF circuit stores a look-up table for an activation function, adjusts a number of logic level combinations of an input distribution signal that correspond to each logic level combination of the output distribution signal, among a plurality of logic level combinations of the output distribution signal, based on an input range of the activation function. The AF circuit selects and outputs the output distribution signal that corresponds to the input distribution signal based on the look-up table. The input range of the activation function is based on a relative number of errors that occur.
    Type: Application
    Filed: January 11, 2021
    Publication date: May 6, 2021
    Applicant: SK hynix Inc.
    Inventors: Seung Yong LEE, Eui Cheol LIM, Choung Ki SONG, Myoung Seo KIM
  • Publication number: 20210089390
    Abstract: A Processing-In-Memory (PIM) device includes a first storage region and a multiplication/accumulation (MAC) calculator. The first storage region configured to store a first data. The MAC operator configured to execute a MAC calculation on the first data and second data in an MAC mode. When an error exists in the first data, the MAC operator compensates multiplication result data generated by a multiplying calculation of the first data and the second data and executes an adding calculation of the compensated multiplication result data.
    Type: Application
    Filed: August 25, 2020
    Publication date: March 25, 2021
    Applicant: SK hynix Inc.
    Inventors: Jeong Jun LEE, Choung Ki SONG