Patents by Inventor Chris Chen
Chris Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220262742Abstract: Embodiments include packages and methods for forming packages which include interposers having a substrate made of a dielectric material. The interposers may also include a redistribution structure over the substrate which includes metallization patterns which are stitched together in a patterning process which includes multiple lateral overlapping patterning exposures.Type: ApplicationFiled: June 4, 2021Publication date: August 18, 2022Inventors: Shang-Yun Hou, Weiming Chris Chen, Kuo-Chiang Ting, Hsien-Pin Hu, Wen-Chih Chiou, Chen-Hua Yu
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Patent number: 11380611Abstract: A method of forming a semiconductor structure includes bonding a first die and a second die to a first side of a first interposer and to a first side of a second interposer, respectively, where the first interposer is laterally adjacent to the second interposer; encapsulating the first interposer and the second interposer with a first molding material; forming a first recess in a second side of the first interposer opposing the first side of the first interposer; forming a second recess in a second side of the second interposer opposing the first side of the second interposer; and filling the first recess and the second recess with a first dielectric material.Type: GrantFiled: July 2, 2020Date of Patent: July 5, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Weiming Chris Chen, Kuo-Chiang Ting, Shang-Yun Hou
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Publication number: 20220127637Abstract: Provided is a polynucleotide the polynucleotide can be used as a WXRE transcriptional regulatory element used to increase the protein expression level of a protein expression system. A protein expression vector or a protein expression systems comprising the above-mentioned WXRE transcriptional regulatory element as well as the use thereof are also provided. The use of the WXRE transcriptional regulatory element can increase the expression level of a heterologous protein greatly with its biological activity unchanged.Type: ApplicationFiled: January 10, 2022Publication date: April 28, 2022Inventors: Zheng Zhang, Xiaolu Li, Yuchen Zhang, Yarong Li, Huifang Dong, Jill Cai, Weichang Zhou, Chris Chen, Lili Mu, Chuanlong Tang
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Patent number: 11254952Abstract: Provided is a polynucleotide, the polynucleotide can be used as a WXRE transcriptional regulatory element used to increase the protein expression level of a protein expression system. A protein expression vector or a protein expression system comprising the above-mentioned WXRE transcriptional regulatory element as well as the use thereof are also provided. The use of the WXRE transcriptional regulatory element can increase the expression level of a heterologous protein greatly with its biological activity unchanged.Type: GrantFiled: August 14, 2019Date of Patent: February 22, 2022Assignee: WuXi Biologies Ireland LimitedInventors: Zheng Zhang, Xiaolu Li, Yuchen Zhang, Yarong Li, Huifang Dong, Jill Cai, Weichang Zhou, Chris Chen, Lili Mu, Chuanlong Tang
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Patent number: 11164855Abstract: A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.Type: GrantFiled: September 17, 2019Date of Patent: November 2, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Weiming Chris Chen, Chi-Hsi Wu, Chih-Wei Wu, Kuo-Chiang Ting, Szu-Wei Lu, Shang-Yun Hou, Ying-Ching Shih, Hsien-Ju Tsou, Cheng-Chieh Li
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Patent number: 11158534Abstract: The present disclosure, in some embodiments, relates to a silicon on insulator (SOI) substrate. The SOI substrate includes a dielectric layer disposed over a first substrate. The dielectric layer has an outside edge aligned with an outside edge of the first substrate. An active layer covers a first annular portion of an upper surface of the dielectric layer. The upper surface of the dielectric layer has a second annular portion that surrounds the first annular portion and extends to the outside edge of the dielectric layer. The second annular portion is uncovered by the active layer.Type: GrantFiled: May 7, 2019Date of Patent: October 26, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Ming-Che Yang, Wei-Kung Tsai, Yong-En Syu, Yeur-Luen Tu, Chris Chen
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Patent number: 11139282Abstract: A semiconductor package structure includes a first package, a second package over the first package, a plurality of connectors between the first package and the second package and a plurality of baffle structures between the first package and the second package. The second package includes a bonding region and a periphery region surrounding the bonding region. The connectors are disposed in the bonding region to provide electrical connections between the first package and the second package. The baffle structures are disposed in the periphery region and are separated from each other.Type: GrantFiled: July 26, 2018Date of Patent: October 5, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kuo-Chiang Ting, Tu-Hao Yu, Ting-Yu Yeh, Chia-Hao Hsu, Weiming Chris Chen, Wan-Yu Lee, Yu-Jie Su
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Publication number: 20210305146Abstract: A method of forming a semiconductor structure includes bonding a first die and a second die to a first side of a first interposer and to a first side of a second interposer, respectively, where the first interposer is laterally adjacent to the second interposer; encapsulating the first interposer and the second interposer with a first molding material; forming a first recess in a second side of the first interposer opposing the first side of the first interposer; forming a second recess in a second side of the second interposer opposing the first side of the second interposer; and filling the first recess and the second recess with a first dielectric material.Type: ApplicationFiled: July 2, 2020Publication date: September 30, 2021Inventors: Weiming Chris Chen, Kuo-Chiang Ting, Shang-Yun Hou
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Publication number: 20210254100Abstract: Provided is a polynucleotide, the polynucleotide can be used as a WXRE transcriptional regulatory element used to increase the protein expression level of a protein expression system. A protein expression vector or a protein expression system comprising the above-mentioned WXRE transcriptional regulatory element as well as the use thereof are also provided. The use of the WXRE transcriptional regulatory element can increase the expression level of a heterologous protein greatly with its biological activity unchanged.Type: ApplicationFiled: August 14, 2019Publication date: August 19, 2021Inventors: Zheng Zhang, Xiaolu Li, Yuchen Zhang, Yarong Li, Huifang Dong, Jill Cai, Weichang Zhou, Chris Chen, Lili Mu, Chuanlong Tang
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Publication number: 20210225666Abstract: A method includes attaching semiconductor devices to an interposer structure, attaching the interposer structure to a first carrier substrate, attaching integrated passive devices to the first carrier substrate, forming an encapsulant over the semiconductor devices and the integrated passive devices, debonding the first carrier substrate, attaching the encapsulant and the semiconductor devices to a second carrier substrate, forming a first redistribution structure on the encapsulant, the interposer structure, and the integrated passive devices, wherein the first redistribution structure contacts the interposer structure and the integrated passive devices, and forming external connectors on the first redistribution structure.Type: ApplicationFiled: January 17, 2020Publication date: July 22, 2021Inventors: Shih Ting Lin, Szu-Wei Lu, Weiming Chris Chen, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
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Publication number: 20210082894Abstract: A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.Type: ApplicationFiled: September 17, 2019Publication date: March 18, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Weiming Chris Chen, Chi-Hsi Wu, Chih-Wei Wu, Kuo-Chiang Ting, Szu-Wei Lu, Shang-Yun Hou, Ying-Ching Shih, Hsien-Ju Tsou, Cheng-Chieh Li
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Publication number: 20210035884Abstract: A semiconductor package includes a redistribution structure, at least one semiconductor device and a plurality of heat dissipation films. The at least one semiconductor device is mounted on the redistribution structure. The plurality of heat dissipation films are disposed on the at least one semiconductor device in a side by side manner and jointly cover an upper surface of the at least one semiconductor device. A manufacturing method of the semiconductor package is also provided.Type: ApplicationFiled: July 29, 2019Publication date: February 4, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ting-Yu Yeh, Cing-He Chen, Kuo-Chiang Ting, Weiming Chris Chen, Chia-Hao Hsu
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Publication number: 20200144155Abstract: A semiconductor package structure includes a substrate, a first semiconductor and a second semiconductor over the substrate, and a multi-TIM structure disposed over the first semiconductor die and the second semiconductor die. The first semiconductor die includes a first heat output and the second semiconductor die includes a second heat output less than the first heat output. The multi-TIM structure includes a first TIM layer disposed over at least a portion of the first semiconductor die and a second TIM layer. A thermal conductivity of the first TIM layer is higher than a thermal conductivity of the second TIM layer. The first TIM layer covers the first semiconductor die.Type: ApplicationFiled: December 23, 2019Publication date: May 7, 2020Inventors: TING-YU YEH, CHIA-HAO HSU, WEIMING CHRIS CHEN, KUO-CHIANG TING, TU-HAO YU, SHANG-YUN HOU
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Publication number: 20200118979Abstract: A semiconductor device includes a first electronic component, a second electronic component, a third electronic component, a plurality of first interconnection structures, and a plurality of second interconnection structures. The second electronic component is between the first electronic component and the third electronic component. The first interconnection structures are between and electrically connected to the first electronic component and the second electronic component. Each of the first interconnection structures has a length along a first direction substantially parallel to a surface of the first electronic component and a width along a second direction substantially parallel to the surface and substantially perpendicular to the first direction. The length is larger than the width. The second interconnection structures are between and electrically connected to the second electronic component and the third electronic component.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Weiming Chris Chen, Tu-Hao Yu, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
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Publication number: 20200111755Abstract: A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first lithograph mask, which covers a first portion of the photo resist. The first portion of the photo resist has a first strip portion exposed in the first light-exposure. The second light-exposure is performed using a second lithograph mask, which covers a second portion of the photo resist. The second portion of the photo resist has a second strip portion exposed in the second light-exposure. The first strip portion and the second strip portion have an overlapping portion that is double exposed. The method further includes developing the photo resist to remove the first strip portion and the second strip portion, etching a dielectric layer underlying the photo resist to form a trench, and filling the trench with a conductive feature.Type: ApplicationFiled: December 5, 2019Publication date: April 9, 2020Inventors: Wen Hsin Wei, Hsien-Pin Hu, Shang-Yun Hou, Weiming Chris Chen
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Publication number: 20200035655Abstract: A semiconductor package structure includes a first package, a second package over the first package, a plurality of connectors between the first package and the second package and a plurality of baffle structures between the first package and the second package. The second package includes a bonding region and a periphery region surrounding the bonding region. The connectors are disposed in the bonding region to provide electrical connections between the first package and the second package. The baffle structures are disposed in the periphery region and are separated from each other.Type: ApplicationFiled: July 26, 2018Publication date: January 30, 2020Inventors: KUO-CHIANG TING, TU-HAO YU, TING-YU YEH, CHIA-HAO HSU, WEIMING CHRIS CHEN, WAN-YU LEE, YU-JIE SU
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Patent number: 10515906Abstract: A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first lithograph mask, which covers a first portion of the photo resist. The first portion of the photo resist has a first strip portion exposed in the first light-exposure. The second light-exposure is performed using a second lithograph mask, which covers a second portion of the photo resist. The second portion of the photo resist has a second strip portion exposed in the second light-exposure. The first strip portion and the second strip portion have an overlapping portion that is double exposed. The method further includes developing the photo resist to remove the first strip portion and the second strip portion, etching a dielectric layer underlying the photo resist to form a trench, and filling the trench with a conductive feature.Type: GrantFiled: August 21, 2017Date of Patent: December 24, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen Hsin Wei, Hsien-Pin Hu, Shang-Yun Hou, Weiming Chris Chen
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Patent number: 10515869Abstract: A semiconductor package structure includes a substrate, a first semiconductor and a second semiconductor over the substrate, and a multi-TIM structure disposed over the first semiconductor die and the second semiconductor die. The first semiconductor die includes a first heat output and the second semiconductor die includes a second heat output less than the first heat output. The multi-TIM structure includes a first TIM layer disposed over at least a portion of the first semiconductor die and a second TIM layer. A thermal conductivity of the first TIM layer is higher than a thermal conductivity of the second TIM layer. The first TIM layer covers the first semiconductor die.Type: GrantFiled: May 29, 2018Date of Patent: December 24, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ting-Yu Yeh, Chia-Hao Hsu, Weiming Chris Chen, Kuo-Chiang Ting, Tu-Hao Yu, Shang-Yun Hou
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Patent number: 10510722Abstract: A semiconductor device includes a first electronic component, a second electronic component and a plurality of interconnection structures. The first electronic component has a first surface. The second electronic component is over the first electronic component, and the second electronic component has a second surface facing the first surface of the first electronic component. The interconnection structures are between and electrically connected to the first electronic component and the second electronic component, wherein each of the interconnection structures has a length along a first direction substantially parallel to the first surface and the second surface, a width along a second direction substantially parallel to the first surface and the second surface and substantially perpendicular to the first direction, and the length is larger than the width of at least one of the interconnection structures.Type: GrantFiled: October 4, 2017Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Weiming Chris Chen, Tu-Hao Yu, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
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Publication number: 20190371700Abstract: A semiconductor package structure includes a substrate, a first semiconductor and a second semiconductor over the substrate, and a multi-TIM structure disposed over the first semiconductor die and the second semiconductor die. The first semiconductor die includes a first heat output and the second semiconductor die includes a second heat output less than the first heat output. The multi-TIM structure includes a first TIM layer disposed over at least a portion of the first semiconductor die and a second TIM layer. A thermal conductivity of the first TIM layer is higher than a thermal conductivity of the second TIM layer. The first TIM layer covers the first semiconductor die.Type: ApplicationFiled: May 29, 2018Publication date: December 5, 2019Inventors: TING-YU YEH, CHIA-HAO HSU, WEIMING CHRIS CHEN, KUO-CHIANG TING, TU-HAO YU, SHANG-YUN HOU