Patents by Inventor Christian Jäger

Christian Jäger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11958871
    Abstract: The present invention relates to novel compounds which are particularly useful as inhibitors of bacterial glutaminyl cyclases (bacQC); pharmaceutical compositions comprising such compounds; compounds and/or pharmaceutical compositions for use in methods for treatment, in particular for use in the treatment of periodontitis and related conditions; as well as to crystals comprising bacterial glutaminyl cyclases, methods for identifying candidate compounds which may associate with the binding pocket of a bacQC and/or are bacQC inhibitors.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: April 16, 2024
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Christian Jäger, Linda Liebe, Daniel Ramsbeck, Miriam Linnert, Stefanie Geissler, Anke Piechotta, Diane Meitzner, Holger Cynis, Mirko Buchholz
  • Publication number: 20240093378
    Abstract: The invention relates to a method for producing a coated body, with a substrate and a coating arranged on the substrate, which coating comprises at least one base layer applied to the substrate and at least one metal carbide-containing layer arranged over the base layer, which layers are applied by means of magnetron sputtering. Furthermore, the invention relates to a coated body produced according to the method.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 21, 2024
    Inventors: Joern Kohlscheen, Christian Bareiss, Horst Jaeger, Patrick Kuhlemann, Christoph Gey
  • Publication number: 20240071395
    Abstract: An apparatus for encoding a first channel and a second channel of an audio input signal including two or more channels to obtain an encoded audio signal according to an embodiment includes a normalizer configured to determine a normalization value for the audio input signal depending on the first channel of the audio input signal and depending on the second channel of the audio input signal. Moreover, the apparatus includes an encoding unit configured to generate a processed audio signal having a first channel and a second channel. The encoding unit is configured to encode the processed audio signal to obtain the encoded audio signal.
    Type: Application
    Filed: October 30, 2023
    Publication date: February 29, 2024
    Inventors: Emmanuel RAVELLI, Markus SCHNELL, Stefan DOEHLA, Wolfgang JAEGERS, Martin DIETZ, Christian HELMRICH, Goran MARKOVIC, Eleni FOTOPOULOU, Markus MULTRUS, Stefan BAYER, Guillaume FUCHS, Juergen HERRE
  • Publication number: 20230352531
    Abstract: A method of manufacturing a vertical power semiconductor device includes forming a drift region in a semiconductor body having a first main surface and a second main surface opposite to the first main surface along a vertical direction, the drift region including platinum atoms, and forming a field stop region in the semiconductor body between the drift region and the second main surface, the field stop region including a plurality of impurity peaks, wherein a first impurity peak of the plurality of impurity peaks is set a larger concentration than a second impurity peak of the plurality of impurity peaks, wherein the first impurity peak includes hydrogen and the second impurity peak includes helium.
    Type: Application
    Filed: July 12, 2023
    Publication date: November 2, 2023
    Inventors: Hans-Joachim Schulze, Christian Jaeger, Moriz Jelinek, Daniel Schloegl, Benedikt Stoib
  • Publication number: 20230307499
    Abstract: A power semiconductor device having a barrier region is provided. A power unit cell of the power semiconductor device has at least two trenches that may both extend into the barrier region. The at least two trenches may both have a respective trench electrode coupled to a control terminal of the power semiconductor device. For example, the trench electrodes are structured to reduce the total gate charge of the power semiconductor device. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by the drift region. The barrier region can be electrically floating.
    Type: Application
    Filed: June 1, 2023
    Publication date: September 28, 2023
    Inventors: Alexander Philippou, Roman Baburske, Christian Jaeger, Johannes Georg Laven, Helmut Maeckel
  • Patent number: 11742384
    Abstract: A vertical power semiconductor device is proposed. The vertical power semiconductor device includes a semiconductor body having a first main surface and a second main surface opposite to the first main surface along a vertical direction. The vertical power semiconductor device further includes a drift region in the semiconductor body. The drift region includes platinum atoms. The vertical power semiconductor device further includes a field stop region in the semiconductor body between the drift region and the second main surface. The field stop region includes a plurality of impurity peaks. A first impurity peak of the plurality of impurity peaks has a larger concentration than a second impurity peak of the plurality of impurity peaks. The first impurity peak includes hydrogen and the second impurity peak includes helium.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: August 29, 2023
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Christian Jaeger, Moriz Jelinek, Daniel Schloegl, Benedikt Stoib
  • Publication number: 20230207673
    Abstract: A power semiconductor device includes: a drift region; a plurality of IGBT cells each having a plurality of trenches extending into the drift region along a vertical direction and laterally confining at least one active mesa which includes an upper section of the drift region; and an electrically floating barrier region of an opposite conductivity type as the drift region and spatially confined, in and against the vertical direction, by the drift region. A total volume of all active mesas is divided into first and second shares, the first share not laterally overlapping with the barrier region and the second share laterally overlapping with the barrier region. The first share carries the load current at least within a range of 0% to 100% of a nominal load current. The second share carries the load current if the load current exceeds at least 0.5% of the nominal load current.
    Type: Application
    Filed: February 21, 2023
    Publication date: June 29, 2023
    Inventors: Antonio Vellei, Markus Beninger-Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Alexander Philippou, Francisco Javier Santos Rodriguez
  • Patent number: 11682700
    Abstract: An power semiconductor device having a barrier region is provided. A power unit cell of the power semiconductor device has at least two trenches that may both extend into the barrier region. The at least two trenches may both have a respective trench electrode coupled to a control terminal of the power semiconductor device. For example, the trench electrodes are structured to reduce the total gate charge of the power semiconductor device. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by the drift region. The barrier region can be electrically floating.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: June 20, 2023
    Assignee: Infineon Technologies AG
    Inventors: Alexander Philippou, Roman Baburske, Christian Jaeger, Johannes Georg Laven, Helmut Maeckel
  • Patent number: 11610986
    Abstract: A power semiconductor switch includes an active cell region with a drift region, an edge termination region, and IGBT cells within the active cell region. Each IGBT cell includes trenches that extend into the drift region and laterally confine mesas. At least one control trench has a control electrode for controlling the load current. At least one dummy trench has a dummy electrode electrically coupled to the control electrode. At least one further trench has a further trench electrode. At least one active mesa is electrically connected to a first load terminal within the active cell region. Each control trench is arranged adjacent to no more than one active mesa. At least one inactive mesa is adjacent to the dummy trench. A cross-trench structure merges each control trench, dummy trench and further trench to each other. The cross-trench structure overlaps at least partially along a vertical direction with the trenches.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: March 21, 2023
    Assignees: Infineon Technologies AG, Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Matteo Dainese, Alexander Philippou, Markus Beninger-Bina, Ingo Dirnstorfer, Erich Griebl, Christian Jaeger, Johannes Georg Laven, Caspar Leendertz, Frank Dieter Pfirsch
  • Patent number: 11594621
    Abstract: A method of processing a power semiconductor device includes: providing a semiconductor body with a drift region of a first conductivity type; forming a plurality of trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction; providing a mask arrangement at the semiconductor body, the mask arrangement having a lateral structure according to which some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction; forming, below bottoms of the exposed trenches, a plurality of doping regions of a second conductivity type complementary to the first conductivity type; removing the mask arrangement; and extending the plurality of doping regions in parallel to the first lateral direction such that the plurality of doping regions overlap and form a barrier region of the second conductivity type adjacent to the bottoms of the exposed trenches.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: February 28, 2023
    Assignee: Infineon Technologies AG
    Inventors: Antonio Vellei, Markus Beninger-Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Alexander Philippou, Francisco Javier Santos Rodriguez
  • Patent number: 11581428
    Abstract: A power semiconductor device includes an active cell region with a drift region of a first conductivity type, a plurality of IGBT cells arranged within the active cell region, each of the IGBT cells includes at least one trench that extends into the drift, an edge termination region surrounding the active cell region, a transition region arranged between the active cell region and the edge termination region, at least some of the IGBT cells are arranged within or extend into the transition region, a barrier region of a second conductivity type, the barrier region is arranged within the active cell region and in contact with at least some of the trenches of the IGBT cells and does not extend into the transition region, and a first load terminal and a second load terminal, the power semiconductor device is configured to conduct a load current along a vertical direction between.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: February 14, 2023
    Assignee: Infineon Technologies AG
    Inventors: Alexander Philippou, Markus Beninger-Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Francisco Javier Santos Rodriguez, Antonio Vellei, Caspar Leendertz, Christian Philipp Sandow
  • Patent number: 11581429
    Abstract: A power semiconductor switch includes an active cell region with a drift region, an edge termination region, and IGBT cells within the active cell region. Each IGBT cell includes trenches that extend into the drift region and laterally confine mesas. At least one control trench has a control electrode for controlling the load current. At least one dummy trench has a dummy electrode electrically coupled to the control electrode. At least one further trench has a further trench electrode. At least one active mesa is electrically connected to a first load terminal within the active cell region. Each control trench is arranged adjacent to no more than one active mesa. At least one inactive mesa is adjacent to the dummy trench. A cross-trench structure merges each control trench, dummy trench and further trench to each other. The cross-trench structure overlaps at least partially along a vertical direction with the trenches.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: February 14, 2023
    Assignees: Infineon Technologies AG, Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Matteo Dainese, Alexander Philippou, Markus Beninger-Bina, Ingo Dirnstorfer, Erich Griebl, Christian Jaeger, Johannes Georg Laven, Caspar Leendertz, Frank Dieter Pfirsch
  • Patent number: 11569392
    Abstract: A power semiconductor diode includes a semiconductor body having first and second main surfaces opposite to each other along a vertical direction. A drift region of a second conductivity type is arranged between an anode region of a first conductivity type and the second main surface. A field stop region of the second conductivity type is arranged between the drift region and the second main surface. A dopant concentration profile of the field stop region along the vertical direction includes a maximum peak. An injection region of the first conductivity type is arranged between the field stop region and the second main surface, with a pn-junction between the injection and field stop regions. A cathode contact region of the second conductivity type is arranged between the field stop region and the second main surface. A first vertical distance between the pn-junction and the maximum peak ranges from 200 nm to 1500 nm.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: January 31, 2023
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Christian Jaeger, Moriz Jelinek, Daniel Schloegl, Benedikt Stoib
  • Publication number: 20220195016
    Abstract: The present invention relates to a peptide with a length of 25 amino acids or less comprising the sequence X1-X2-X3-X4-X5-X6-X7-X8-X9-X10-X11-X12-X13 (SEQ ID No: 1) as well as to A peptide with a length of 25 amino acids or less comprising the sequence X1-X2-X3-X4-X5-X6-X7-X8-X9-X10-X11-X12-X13-X14 (SEQ ID No: 2). The present invention further relates to a nanostructure comprising a nucleic acid scaffold and at least two peptide moieties, wherein the sequence of each of the at least two peptide moieties is independently selected from the sequence of the peptide of the invention as well as pharmaceutical compositions, nucleic acids, methods and uses related thereto.
    Type: Application
    Filed: April 17, 2020
    Publication date: June 23, 2022
    Inventors: David Michael Smith, Christin Möser, Thomas Grunwald, Leila Issmail, Christian Jäger, Martin Kleinschmidt, Daniel Ramsbeck, Mirko Buchholz
  • Publication number: 20220085215
    Abstract: A power semiconductor diode includes a semiconductor body having first and second main surfaces opposite to each other along a vertical direction. A drift region of a second conductivity type is arranged between an anode region of a first conductivity type and the second main surface. A field stop region of the second conductivity type is arranged between the drift region and the second main surface. A dopant concentration profile of the field stop region along the vertical direction includes a maximum peak. An injection region of the first conductivity type is arranged between the field stop region and the second main surface, with a pn-junction between the injection and field stop regions. A cathode contact region of the second conductivity type is arranged between the field stop region and the second main surface. A first vertical distance between the pn-junction and the maximum peak ranges from 200 nm to 1500 nm.
    Type: Application
    Filed: September 3, 2021
    Publication date: March 17, 2022
    Inventors: Hans-Joachim Schulze, Christian Jaeger, Moriz Jelinek, Daniel Schloegl, Benedikt Stoib
  • Patent number: 11257914
    Abstract: A semiconductor die includes a semiconductor body having first and second active portions. The first active portion includes first source regions. The second active portion includes second source regions. A gate structure extends from a first surface into the semiconductor body and has a longitudinal gate extension along a lateral first direction. A first load pad and the first source regions are electrically connected. A second load pad and the second source regions are electrically connected. A gap laterally separates the first and second load pads. A lateral longitudinal extension of the gap is parallel to the first direction or deviates therefrom by not more than 60 degree. A connection structure electrically connects the first and second load pads. The connection structure is formed in a groove extending from the first surface into the semiconductor body and/or in a wiring layer formed on the first surface.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: February 22, 2022
    Assignee: Infineon Technologies AG
    Inventors: Vera Van Treek, Roman Baburske, Christian Jaeger, Christian Robert Mueller, Franz-Josef Niedernostheide, Frank Dieter Pfirsch, Alexander Philippou, Judith Specht
  • Publication number: 20210320174
    Abstract: A vertical power semiconductor device is proposed. The vertical power semiconductor device includes a semiconductor body having a first main surface and a second main surface opposite to the first main surface along a vertical direction. The vertical power semiconductor device further includes a drift region in the semiconductor body. The drift region includes platinum atoms. The vertical power semiconductor device further includes a field stop region in the semiconductor body between the drift region and the second main surface. The field stop region includes a plurality of impurity peaks. A first impurity peak of the plurality of impurity peaks has a larger concentration than a second impurity peak of the plurality of impurity peaks. The first impurity peak includes hydrogen and the second impurity peak includes helium.
    Type: Application
    Filed: March 30, 2021
    Publication date: October 14, 2021
    Inventors: Hans-Joachim Schulze, Christian Jaeger, Moriz Jelinek, Daniel Schloegl, Benedikt Stoib
  • Publication number: 20210313460
    Abstract: A power semiconductor switch includes an active cell region with a drift region, an edge termination region, and IGBT cells within the active cell region. Each IGBT cell includes trenches that extend into the drift region and laterally confine mesas. At least one control trench has a control electrode for controlling the load current. At least one dummy trench has a dummy electrode electrically coupled to the control electrode. At least one further trench has a further trench electrode. At least one active mesa is electrically connected to a first load terminal within the active cell region. Each control trench is arranged adjacent to no more than one active mesa. At least one inactive mesa is adjacent to the dummy trench. A cross-trench structure merges each control trench, dummy trench and further trench to each other. The cross-trench structure overlaps at least partially along a vertical direction with the trenches.
    Type: Application
    Filed: June 17, 2021
    Publication date: October 7, 2021
    Inventors: Matteo Dainese, Alexander Philippou, Markus Beninger-Bina, Ingo Dirnstorfer, Erich Griebl, Christian Jaeger, Johannes Georg Laven, Caspar Leendertz, Frank Dieter Pfirsch
  • Patent number: 11104999
    Abstract: A coated tool has a substrate and a hard material coating deposited on the substrate. The hard material coating has a layer structure in the following order, starting from the substrate: a titanium nitride layer, a titanium boron nitride transition layer, and a titanium diboride layer. The titanium boron nitride transition layer has a boron content that increases from the titanium nitride layer in the direction of the titanium diboride layer. The boron content does not exceed 15 at %.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: August 31, 2021
    Assignee: CERATIZIT Austria Gesellschaft m.b.H.
    Inventors: Christoph Czettl, Josef Thurner, Markus Lechleitner, Christian Jaeger
  • Patent number: 11075290
    Abstract: A power semiconductor device includes an active region surrounded by an inactive termination region each formed by part of a semiconductor body. The active region conducts load current between first and second load terminals. At least one power cell has trenches extending into the semiconductor body adjacent to each other along a first lateral direction and having a stripe configuration that extends along a second lateral direction into the active region. The trenches spatially confine a plurality of mesas each having at least one first type mesa electrically connected to the first load terminal and configured to conduct at least a part of the load current, and at least one second type mesa configured to not conduct the load current. A decoupling structure separates at least one of the second type mesas into a first section in the active region and a second section in the termination region.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: July 27, 2021
    Assignees: Infineon Technologies AG, Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Matteo Dainese, Alexander Philippou, Markus Bina, Ingo Dirnstorfer, Erich Griebl, Christian Jaeger, Johannes Georg Laven, Caspar Leendertz, Frank Dieter Pfirsch