Abstract: A thermal finite-state-automaton includes system states and transitions between the system states. The system states may be based on a combination of network parameters for communicating through the wireless communication system and UE processing parameters. A default state is for operation of the UE at a sustainable performance configuration level for the network parameters and the UE processing parameters to maintain a UE temperature below a first temperature threshold. A high state is for operation of the UE during up to a maximum time duration at a peak performance configuration level for the network parameters and the UE processing parameters. A recovery state is for operation of the UE during at least a minimum time duration at a reduced performance configuration level for the network parameters and the UE processing parameters. An emergency shutdown state is triggerable by the UE temperature exceeding a second temperature threshold.

Abstract: A thermal finite-state-automaton includes system states and transitions between the system states. The system states may be based on a combination of network parameters for communicating through the wireless communication system and UE processing parameters. A default state is for operation of the UE at a sustainable performance configuration level for the network parameters and the UE processing parameters to maintain a UE temperature below a first temperature threshold. A high state is for operation of the UE during up to a maximum time duration at a peak performance configuration level for the network parameters and the UE processing parameters. A recovery state is for operation of the UE during at least a minimum time duration at a reduced performance configuration level for the network parameters and the UE processing parameters. An emergency shutdown state is triggerable by the UE temperature exceeding a second temperature threshold.

Abstract: A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.

Abstract: Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor. An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric in comparison with other transistors on the same integrated circuit arrangement. As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions of the tunnel field effect transistor.

Abstract: Implementations are presented herein that include a plurality of on-chip monitor circuits and a controller. Each of the plurality of on-chip monitor circuits is configured to measure a parameter of a semiconductor chip. The controller is coupled to the plurality of on-chip monitor circuits. The controller is configured to receive a measurement result from at least one of the plurality of on-chip monitor circuits and to control a calibration of another one of the plurality of on-chip monitor circuits in accordance with the measurement result.

Abstract: Implementations are presented herein that include a test circuit and a reference circuit.

Abstract: One or more embodiments relate to an apparatus comprising: a first transistor including a channel in a fin; and a second transistor including a channel in a fin, the channel of the first transistor being doped with a first dopant of a first polarity and counter-doped with a second dopant of a second polarity opposite to the first polarity, a concentration of the first dopant being approximately equal to a concentration of the second dopant, wherein the first transistor and the second transistor are of a same conductivity type.

Abstract: Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor. An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric in comparison with other transistors on the same integrated circuit arrangement. As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions of the tunnel field effect transistor.

Abstract: According to one aspect of this disclosure, a circuit arrangement is provided, the circuit arrangement including an electronic component coupled to at least one common power supply node and configured to provide a first signal having a variation in time that is based on power supply via the at least one common power supply node; a detecting circuit coupled to the electronic component, the detecting circuit being configured to detect the first signal and to provide a digital switch array control signal based on the variation in time of the first signal; and a switch array coupled between the at least one common power supply node and at least one power supply source, the switch array being configured to control the power supply via the at least one common power supply node based on the digital switch array control signal.

Abstract: An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric (GD1) in comparison with other transistors (T2) on the same integrated circuit arrangement (10). As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions (D1, S1) of the tunnel field effect transistor.

Abstract: One or more embodiments relate to a method comprising: raising a potential of a first bit line and a second bit line; switching on a first n-channel access transistor coupled between the first bit line and a first node of a first inverter; switching on a second n-channel access transistor coupled between the second bit line and a second node of a second inverter; and reading a static random access memory (SRAM) cell including the first inverter and the second inverter by sensing a potential on the first bit line and a potential on the second bit line.

Abstract: According to one aspect of this disclosure, a circuit arrangement is provided, the circuit arrangement including an electronic component coupled to at least one common power supply node and configured to provide a first signal having a variation in time that is based on power supply via the at least one common power supply node; a detecting circuit coupled to the electronic component, the detecting circuit being configured to detect the first signal and to provide a digital switch array control signal based on the variation in time of the first signal; and a switch array coupled between the at least one common power supply node and at least one power supply source, the switch array being configured to control the power supply via the at least one common power supply node based on the digital switch array control signal.

Abstract: One or more embodiments relate to an apparatus comprising: a first transistor including a channel in a fin; and a second transistor including a channel in a fin, the channel of the first transistor being doped with a first dopant of a first polarity and counter-doped with a second dopant of a second polarity opposite to the first polarity, a concentration of the first dopant being approximately equal to a concentration of the second dopant, wherein the first transistor and the second transistor are of a same conductivity type.

Abstract: One or more embodiments relate to an apparatus comprising: a first transistor including a fin; and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor.

Abstract: The present disclosure relates to on-chip self calibrating delay monitoring circuitry.

Abstract: Embodiments relate to micromachine structures. In one embodiment, a micromachine structure includes a first electrode, a second electrode, and a sensing element. The sensing element is mechanically movable and is disposed intermediate the first and second electrodes and adapted to oscillate between the first and second electrodes. Further, the sensing element includes a FinFET structure having a height and a width, the height being greater than the width.

Abstract: Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.

Abstract: One or more embodiments of the invention relate to a method comprising: treating a fin of a first n-channel access transistor in a static random access memory cell to have a lower charge carrier mobility than a fin of a first n-channel pull-down transistor in a first inverter in the memory cell, the first n-channel access transistor being coupled between a first bit line and a first node of the first inverter; and treating a fin of a second n-channel access transistor in the memory cell to have a lower charge carrier mobility than a fin of a second n-channel pull-down transistor in a second inverter in the memory cell, the second n-channel access transistor being coupled between a second bit line and a second node of the second inverter.

Abstract: Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.

Abstract: Embodiments relate to a bipolar transistor that includes a body region having a fin structure. At least one terminal region may be formed over at least a portion of the body region. The at least one terminal region may be formed as an epitaxially grown region. Embodiments also relate to a vertically integrated electronic device that includes a first terminal region, a second terminal region and a third terminal region. The second terminal region may be arranged over at least a portion of the third terminal region, and at least two of the first, second and third terminal regions may be formed as epitaxially grown regions.