Abstract: A circuit arrangement may include a scan test input stage having a test input for receiving a test signal, wherein the scan test input stage can be switched in high-impedance state; a data input stage having a data input for receiving a data signal, wherein the data input stage can be switched in high-impedance state. The circuit arrangement may further include a latch coupled to at least one output of the scan test input stage and to at least one output of the data input stage; and a drive circuit, which is configured to generate a pulsed clock signal for the data input stage and a signal for driving the scan test input stage.

Abstract: P-type multi gate field effect transistor access devices are adapted to be coupled to a memory cell to provide access to the memory cell. A method is described that uses a power switch to switch off address decoding circuitry allowing word lines to float toward a high supply voltage, turning off the p-type multi gate field effect transistor access devices.

Abstract: The invention relates to a label identification system comprised of a transmitting-receiving unit and of identification labels on which the identification information is stored in the form of a digital identification information word. The provision of a circuit on the identification label in the form of a circuit arrangement, which is prefabricated using a polymer technique and on which the identification information is subsequently placed by the offset printing of conductor tracks, enables the provision of an identification label involving a minimal consumption of energy during inexpensive mass production. The bulk of the identification information processing is transferred to the transmitting-receiving unit.

Abstract: A method and an apparatus for switching on a voltage supply of a voltage domain of a semiconductor circuit is disclosed. A voltage supply is connected to a supply voltage of the semiconductor circuit by means of a switchable element. The switchable element is activated in such a way that, for switching on the voltage supply of the voltage domain, a current through the switchable element rises progressively with at least one intermediate value, in particular stepwise manner.

Abstract: A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.

Abstract: A first SOI field effect transistor with predetermined transistor properties, comprising: a laterally delimited layer sequence with a gate-insulating layer and a gate region on an undoped substrate; a spacer layer having a predetermined thickness on at least a portion of the sidewalls of the laterally delimited layer sequence; and two source/drain regions in two surface regions of the substrate which are adjoined by the spacer layer, with a predetermined dopant concentration profile, the layer sequence and the spacer layer forming a shading structure that prevents dopant from being introduced into a surface region of the substrate between the two source/drain regions during the production of the first SOI field effect transistor, wherein the predetermined transistor properties of the first SOI field effect transistor are set by setting the thickness of the spacer layer and by the dopant concentration profile.

Abstract: A multi-gate field effect transistor power switch is used to selectively couple a circuit to a supply voltage. In various embodiments, both n and p-type multi-gate field effect transistor power switches may be used to couple sub-circuits of varying granularity to different voltage supplies.

Abstract: Method for producing a first SOI field effect transistor with predetermined transistor properties by forming a laterally delimited layer sequence with a gate-insulating layer and a gate region on an undoped substrate, forming a spacer layer having a predetermined thickness, on at least a portion of the sidewalls of the laterally delimited layer sequence, and forming two source/drain regions having a predetermined dopant concentration profile, by introducing dopant into two surface regions of the substrate which are adjoined by the spacer layer, the layer sequence and the spacer layer forming a shading structure that prevents dopant from being introduced into a surface region of the substrate between the two source/drain regions, wherein the predetermined transistor properties of the first SOI field effect transistor are set by setting the thickness of the spacer layer and by setting the dopant concentration profile.

Abstract: A circuit includes a plurality of first MuGFET devices supported by a substrate and having a first performance level. A plurality of second MuGFET devices is supported by the substrate and have a second performance level. The first and second devices in one embodiment are arranged in separate areas that facilitate different processing of the first and second devices to tailor their performance characteristics. In one embodiment, the circuit is an SRAM having pull down transistors with higher performance.

Abstract: In an embodiment of the invention, a CMOS circuit arrangement is provided. The CMOS circuit arrangement includes a PMOS logic circuit providing a logic function, having PMOS field effect transistors, wherein a first operating potential is fed to an input of a PMOS logic circuit, an NMOS logic circuit providing the logic function, having NMOS field effect transistors, a first clock transistor, the first source/drain terminal of which is coupled to an input of the NMOS logic circuit, wherein a clock signal is applied to the gate terminal of the first clock transistor, and wherein a second operating potential is fed to the second source/drain terminal. An output of the PMOS logic circuit and an output of the NMOS logic circuit are coupled to one another. Furthermore, an inverter circuit is coupled to the output of the PMOS logic circuit and to the output of the NMOS logic circuit.

Abstract: An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.

Abstract: A semiconductor circuit arrangement and a method for temperature detection is disclosed. One embodiment includes a semiconductor substrate, on which is formed a first insulating layer and thereon a thin active semiconductor region, which is laterally delimited by a second insulating layer. In the active semiconductor region, a first and second doping zone are formed on the surface of the first insulating layer for the definition of a channel zone, wherein there is formed at the surface of the channel zone a gate dielectric and thereon a control electrode for the realization of a field effect transistor. In the active semiconductor region, a diode doping zone is formed on the surface of the first insulating layer, which zone realizes a measuring diode via a diode side area with the first or second doping zone and is delimited by the second insulating layer at its further side areas.

Abstract: Noise-reducing transistor arrangement having first and second field effect transistors (FETs) having source terminals coupled together, drain terminals coupled together, and control terminals for application of a first or second signal. A clock generator unit is configured to provide the first and second signals alternately to the FETs with an alternating frequency which is at least as great as the cut-off frequency of the noise characteristic of the FETs, or with a reciprocal alternating frequency which is less than a mean lifetime of an occupation state of a defect in the boundary region between channel region and gate insulating layer of the FETs. The first signal is applied to the control terminal of the first FET and, simultaneously, the second signal to the control terminal of the second FET. The second signal is applied to the control terminal of the first FET and, simultaneously, the first signal to the control terminal of the second FET.

Abstract: Pulse-generator circuit for generating an input signal for a flip-flop circuit from a clock-pulse signal and a data signal. The circuit includes a control unit for controlling a clock-pulse field effect transistor, a logic field effect transistor and a feedback field effect transistor. To generate the input signal, the control unit is configured in such a way that the clock-pulse field effect transistor is controlled chronologically after the logic field effect transistor and the feedback field effect transistor, thus generating the flip-flop signal.

Abstract: An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.

Abstract: A pulsed static flip-flop comprises a first logic device which combines a logic signal with a pulsed signal and outputs a set signal, a second logic device which logically combines the logic signal with a complementary pulsed signal and outputs a reset signal; and a latch device comprising storage means which hold a logic hold level to be tapped off as a stored logic state of the logic signal. The logic hold level is adjustable to a first logic level by a first push-pull transistor controlled by the set signal and to a second logic level by a second push-pull transistor controlled by the reset signal.

Abstract: A clock transistor and a second operating potential functioning as a circuit breaker, are mounted between the outlet of an NMOS logic circuit.

Abstract: A method and an apparatus for switching on a voltage supply of a voltage domain of a semiconductor circuit is disclosed. A voltage supply is connected to a supply voltage of the semiconductor circuit by means of a switchable element. The switchable element is activated in such a way that, for switching on the voltage supply of the voltage domain, a current through the switchable element rises progressively with at least one intermediate value, in particular stepwise manner.

Abstract: The invention relates to an electronic component that can be operated by means of an alternating voltage. Said component includes at least one input, at least one output and a pair of electronic sub-components with an identical function. The input(s) of the electronic component is/are coupled to a respective input of the electronic sub-components with an identical function and the output(s) of the electronic component is/are coupled to a respective output of said electronic sub-components. In addition, the electronic component is configured in such a way that at least one output only one output signal of the first sub-component of the pair of functionally identical electronic components can be picked up during a first half-wave of an alternating voltage, whereas only one output signal of the second sub-component of the pair of functionally identical electronic can be picked up during the second half-wave of the alternating voltage.

Abstract: A frequency-divider circuit arrangement having a power supply, a first clock signal, a second clock signal, a first switch unit, a first capacitance which is connected downstream from the first switch unit is disclosed. A second switch unit is connected downstream from the first capacitance and is controlled by the second clock signal, a second capacitance is connected downstream from the second switch unit and is connected in parallel to the first capacitance, a clock-signal control unit, a capacitance discharge device and a capacitance discharge device control unit.