Patents by Inventor Christopher James Kapusta

Christopher James Kapusta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11309304
    Abstract: An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: April 19, 2022
    Assignee: General Electric Company
    Inventors: James Sabatini, Christopher James Kapusta, Glenn Forman
  • Publication number: 20220070996
    Abstract: A power overlay (POL) module includes a semiconductor device having a first side and an opposing second side, a dielectric sheet having a first side coupled to the semiconductor device second side, and an opposing second side, the dielectric sheet defining an aperture therethrough. The POL module also includes a first conductive layer disposed on the second side of the dielectric sheet and electrically coupled through the aperture to the semiconductor device second surface, a first conductive plate having a first side, and an opposing second side coupled to the first surface of the semiconductor device. The POL module further includes a first heat sink coupled the first side of the conductive plate and a first thermal interface layer disposed between the first conductive plate and the first heat sink.
    Type: Application
    Filed: August 28, 2020
    Publication date: March 3, 2022
    Inventors: David Richard Esler, Christopher James Kapusta, Arun V. Gowda, Weijun Yin, Liqiang Yang, Richard Anthony Eddins
  • Publication number: 20210375813
    Abstract: An electronics package includes an electrically insulating substrate having a first surface and a second surface, an adhesive layer positioned on the first surface of the electrically insulating substrate, and an electrical component having a top surface coupled to the adhesive layer on a surface thereof opposite the electrically insulating substrate, the electrical component having contact pads on the top surface. Vias are formed through the electrically insulating substrate and the adhesive layer at locations corresponding to the contact pads by way of a mechanical punching operation, with each of the vias having a via wall extending from the second surface of the electrically insulating substrate to a respective contact pad. At each via, the electrically insulating substrate comprises a protrusion extending outwardly from the first surface thereof so as to cover at least part of the adhesive layer in forming part of the via wall.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 2, 2021
    Applicant: General Electric Company
    Inventors: Christopher James Kapusta, Youichi Nishihara
  • Publication number: 20210325348
    Abstract: A system includes a sensor comprising a sensor bonding layer disposed on a surface of the sensor, wherein the sensor bonding layer is a metallic alloy. An inlay includes a planar outer surface, wherein the inlay may be disposed on a curved surface of a structure. A structure bonding layer may be disposed on the planar outer surface of the inlay, wherein the structure bonding layer is a metallic alloy. The sensor bonding layer is coupled to the structure bonding layer via a metallic joint, and the sensor is configured to sense data of the structure through the metallic joint, the structure bonding layer, and the sensor bonding layer. The inlay comprises at least one of a modulus of elasticity, a shape, a thickness, and a size configured to reduce strain transmitted to the sensor.
    Type: Application
    Filed: June 29, 2021
    Publication date: October 21, 2021
    Applicant: General Electric Company
    Inventors: Joseph Alfred Iannotti, Christopher James Kapusta, David Richard Esler
  • Patent number: 11079359
    Abstract: A system includes a structure bonding layer and a sensor. The structure bonding layer is disposed on a structure. The structure bonding layer is a metallic alloy. The sensor includes a non-metallic wafer and a sensor bonding layer disposed on a surface of the non-metallic wafer. The sensor bonding layer is a metallic alloy. The sensor bonding layer is coupled to the structure bonding layer via a metallic joint, and the sensor is configured to sense data of the structure through the metallic joint, the structure bonding layer, and the sensor bonding layer.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: August 3, 2021
    Assignee: General Electric Company
    Inventors: Joseph Alfred Iannotti, Christopher James Kapusta, David Richard Esler
  • Publication number: 20210204397
    Abstract: An electronics package is disclosed. The electronics package includes a first radio frequency (RF) substrate layer, a second RF substrate layer, and a plurality of conductive layers disposed adjacent to at least one of the first RF substrate layer and the second RF substrate layer and including an inner conductive layer disposed between and adjacent to both the first RF substrate layer and the second RF substrate layer. The inner conductive layer bonds the first RF substrate layer to the second RF substrate layer. The electronics package also includes a plurality of conductive interconnects extending through the first RF substrate layer and the second RF substrate layer and electrically coupled between at least two of the plurality of conductive layers.
    Type: Application
    Filed: December 30, 2019
    Publication date: July 1, 2021
    Inventors: Christopher James Kapusta, Stanton Earl Weaver, JR., Joseph Alfred Iannotti
  • Publication number: 20210104812
    Abstract: A wireless access point is disclosed. The wireless access point includes a substrate, an antenna structure disposed on the substrate and configured to transmit and receive wireless electromagnetic communication signals, and a fiber-optic interface disposed on the substrate and communicatively coupled to the antenna structure and a fiber-optic cable. The fiber-optic interface is configured to transmit and receive optical communication signals through the fiber-optic cable.
    Type: Application
    Filed: December 13, 2019
    Publication date: April 8, 2021
    Inventors: Christopher James Kapusta, Joseph Alfred Iannotti, Stanton Earl Weaver, Glen Peter Koste
  • Patent number: 10957832
    Abstract: A light emitting semiconductor (LES) device having desirable thermal performance characteristics is disclosed. The LES device includes an insulating substrate layer having a plurality of vias formed therein and at least one LES chip mounted on the insulating substrate layer, with each of the LES chips(s) including an active surface including a light emitting area configured to emit light therefrom and a back surface positioned on a top surface of the insulating substrate layer and including connection pads thereon. A conductor layer is positioned on a bottom surface of the insulating substrate layer and in the vias, the conductor layer in direct contact with the connection pads of the LES chip(s) so as to be electrically and thermally connected thereto. An encapsulant is positioned adjacent the top surface of the insulating substrate layer and surrounding at least part of the LES chip(s), the encapsulant comprising a light transmitting material.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: March 23, 2021
    Assignee: General Electric Company
    Inventors: Christopher James Kapusta, Risto Ilkka Sakari Tuominen, Kaustubh Ravindra Nagarkar
  • Publication number: 20210017979
    Abstract: A sensor system for monitoring a condition of a piston rod includes an interrogator system having a first coil winding coupled to a housing and radially spaced from the piston rod such that a gap is defined between the first coil winding and the piston rod. A second coil winding is coupled to the piston rod and is inductively coupled to the first coil winding. The second coil winding is configured to communicate with the first coil winding through a range of linear movement of the piston rod relative to the housing. A sensor is coupled to the second coil winding. The sensor is configured to measure a characteristic associated with the piston rod and generate a current in the second coil winding to transmit, via the inductive coupling with the first coil winding, an electrical output signal associated with the characteristic to the interrogator system.
    Type: Application
    Filed: July 19, 2019
    Publication date: January 21, 2021
    Inventors: Joseph Alfred Iannotti, Christopher James Kapusta, Marco Francesco Aimi
  • Publication number: 20210013866
    Abstract: A wafer level assembly is disclosed. The wafer level assembly includes a device wafer, and a plurality of electrodes disposed on the device wafer, wherein the device wafer the plurality of electrodes form a surface acoustic wave (SAW) device, a plurality of device pads disposed on the device wafer, wherein each of the plurality of electrodes are coupled to one of the device pads, a cap wafer coupled to the device wafer through a seal layer, the cap wafer having a plurality of contact pads and a plurality of interconnect pads integral with a surface of the cap wafer, wherein each of the plurality of contact pads is coupled to one of the plurality of interconnect pads, and a plurality of conductive interconnects, wherein each of the plurality of conductive interconnects is coupled between one of the plurality of device pads and one of the plurality of interconnect pads.
    Type: Application
    Filed: July 12, 2019
    Publication date: January 14, 2021
    Inventors: Joseph Alfred Iannotti, Christopher James Kapusta
  • Patent number: 10892237
    Abstract: Methods of fabricating a semiconductor device are provided. The method includes providing a plurality of semiconductor devices. The method further includes disposing a dielectric dry film on the plurality of semiconductor devices, wherein the dielectric dry film is patterned such that openings in the patterned dielectric dry film are aligned with conductive pads of each of the plurality of semiconductor devices.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: January 12, 2021
    Assignee: General Electric Company
    Inventors: Stephen Daley Arthur, Liangchun Yu, Nancy Cecelia Stoffel, David Richard Esler, Christopher James Kapusta
  • Patent number: 10892231
    Abstract: An electronics package includes a support substrate, an electrical component having a first surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and sidewalls of the electrical component. The insulating structure has a sloped outer surface. A conductive layer encapsulates the electrical component and the sloped outer surface of the insulating structure. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is coupled to the conductive layer through at least one via in the support substrate.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: January 12, 2021
    Assignee: General Electric Company
    Inventors: Christopher James Kapusta, Raymond Albert Fillion, Risto Ilkka Sakari Tuominen, Kaustubh Ravindra Nagarkar
  • Patent number: 10804115
    Abstract: An electronics package includes an insulating substrate, an electrical component having an active surface coupled to a first surface of the insulating substrate, and an insulating structure disposed adjacent the electrical component on the first surface of the insulating substrate. A first wiring layer is formed on a top surface of the insulating structure and extends down at least one sloped side surface of the insulating structure. A second wiring layer is formed on a second surface of the insulating substrate. The second wiring layer extends through a plurality of vias in the insulating substrate to electrically couple at least one contact pad on the active surface of the electrical component to the first wiring layer.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: October 13, 2020
    Assignee: General Electric Company
    Inventors: Christopher James Kapusta, Raymond Albert Fillion, Risto Ilkka Sakari Tuominen, Kaustubh Ravindra Nagarkar
  • Patent number: 10804174
    Abstract: A non-magnetic hermetic package includes walls that surround an open cavity, with a generally planar non-magnetic and metallic seal ring disposed in a continuous loop around upper edges of the walls; a sensitive component that is bonded within the cavity; and a non-magnetic lid that is sealed to the seal ring to close the cavity by a metallic seal.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: October 13, 2020
    Assignee: General Electric Company
    Inventors: Christopher James Kapusta, Marco Francesco Aimi
  • Patent number: 10804116
    Abstract: An electronics package includes an insulating substrate, an electrical component having a back surface coupled to a first surface of the insulating substrate, and an insulating structure surrounding at least a portion of a perimeter of the electrical component. A first wiring layer extends from the first surface of the insulating substrate and over a sloped side surface of the insulating structure to electrically couple with at least one contact pad on an active surface of the electrical component. A second wiring layer is formed on a second surface of the insulating substrate and extends through at least one via therein to electrically couple with the first wiring layer.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: October 13, 2020
    Assignee: General Electric Company
    Inventors: Christopher James Kapusta, Raymond Albert Fillion, Risto Ilkka Sakari Tuominen, Kaustubh Ravindra Nagarkar
  • Patent number: 10784576
    Abstract: A beam former module includes a package base and an interconnect structure formed within the package base. The beam former module also includes a first true time delay (TTD) module attached to the package base. The first TTD module includes a plurality of switching elements configured to define a signal transmission path between a signal input and a signal output of the first TTD module by selectively activating a plurality of time delay lines. The signal input and the signal output of the first TTD module are electrically coupled to the interconnect structure. In some embodiments, the interconnect structure includes at least one TTD meander line and at least one of the time delay lines of the first TTD module is electrically coupled to the at least one TTD meander line.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: September 22, 2020
    Assignee: General Electric Company
    Inventors: Joseph Alfred Iannotti, Christopher James Kapusta
  • Patent number: 10770382
    Abstract: A modular electronics package is disclosed that includes a first and second electronics packages, with each of the first and second electronics packages including a metallized insulating substrate and a solid-state switching device positioned on the metallized insulating substrate, the solid-state switching device comprising a plurality of contact pads electrically coupled to the first conductor layer of the metallized insulating substrate. A conductive joining material is positioned between the first electronics package and the second electronics package to electrically connect them together. The first electronics package and the second electronics package are stacked with one another to form a half-bridge unit cell, with the half-bridge unit cell having a current path through the solid-state switching device in the first electronics package and a close coupled return current path through the solid-state switching device in the second electronics package in opposite flow directions.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: September 8, 2020
    Assignee: General Electric Company
    Inventors: Christopher James Kapusta, Ramanujam Ramabhadran, Kum-Kang Huh, Brian Lynn Rowden, Glenn Scott Claydon, Ahmed Elasser
  • Publication number: 20200194387
    Abstract: A semiconductor device is provided. The semiconductor device includes an electric field (E-field) suppression layer formed over a termination region. The E-field suppression layer is patterned with openings over metal contact areas. The E-field suppression layer has a thickness such that an electric field strength above the E-field suppression layer is below a dielectric strength of an adjacent material when the semiconductor device is operating at or below a maximum voltage.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 18, 2020
    Inventors: Stephen Daley Arthur, Liangchun Yu, Nancy Cecelia Stoffel, David Richard Esler, Christopher James Kapusta
  • Publication number: 20200194388
    Abstract: Methods of fabricating a semiconductor device are provided. The method includes providing a plurality of semiconductor devices. The method further includes disposing a dielectric dry film on the plurality of semiconductor devices, wherein the dielectric dry film is patterned such that openings in the patterned dielectric dry film are aligned with conductive pads of each of the plurality of semiconductor devices.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 18, 2020
    Inventors: Stephen Daley Arthur, Liangchun Yu, Nancy Cecelia Stoffel, David Richard Esler, Christopher James Kapusta
  • Publication number: 20200176360
    Abstract: A modular electronics package is disclosed that includes a first and second electronics packages, with each of the first and second electronics packages including a metallized insulating substrate and a solid-state switching device positioned on the metallized insulating substrate, the solid-state switching device comprising a plurality of contact pads electrically coupled to the first conductor layer of the metallized insulating substrate. A conductive joining material is positioned between the first electronics package and the second electronics package to electrically connect them together. The first electronics package and the second electronics package are stacked with one another to form a half-bridge unit cell, with the half-bridge unit cell having a current path through the solid-state switching device in the first electronics package and a close coupled return current path through the solid-state switching device in the second electronics package in opposite flow directions.
    Type: Application
    Filed: November 29, 2018
    Publication date: June 4, 2020
    Inventors: Christopher James Kapusta, Ramanujam Ramabhadran, Kum-Kang Huh, Brian Lynn Rowden, Glenn Scott Claydon, Ahmed Elasser