Patents by Inventor Christopher James Kapusta
Christopher James Kapusta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11950394Abstract: The disclosure relates to an apparatus and method for liquid cooling of an electronic component. A housing includes an insertion slot and defines at least one component chamber for carrying the electronic component. A fluid inlet and fluid outlet are provided on the housing. A liquid coolant circuit passes through the housing at least from the inlet to the outlet.Type: GrantFiled: October 12, 2021Date of Patent: April 2, 2024Assignee: GE Aviation Systems LLCInventors: Brian Magann Rush, Christopher James Kapusta, David Richard Esler, Liang Yin, Richard Anthony Eddins, Judd Everett Swanson, Liqiang Yang
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Publication number: 20230420901Abstract: The disclosure relates to an apparatus for connecting an electronic component to a conductor. A housing includes at least one slot and defines at least one component chamber for carrying the electronic component. A liquid coolant can pass through the housing. A pair of conductive members extends from the housing through the at least one slot and can be releasably inserted into a channel defined in a support assembly. The support assembly facilitates an electrical connection between the conductive members and corresponding conductive contact members connected to a respective power supply or electrical load. The support assembly can provide an inward sealing force to a seal on the housing circumscribing the pair of conductive members.Type: ApplicationFiled: June 22, 2022Publication date: December 28, 2023Inventors: Christopher James Kapusta, David Richard Esler, Arun Virupaksha Gowda, Brian Magann Rush, Liang Yin, Richard Anthony Eddins, Liqiang Yang, Judd Everett Swanson
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Patent number: 11824030Abstract: An electronics package includes an electrically insulating substrate having a first surface and a second surface, an adhesive layer positioned on the first surface of the electrically insulating substrate, and an electrical component having a top surface coupled to the adhesive layer on a surface thereof opposite the electrically insulating substrate, the electrical component having contact pads on the top surface. Vias are formed through the electrically insulating substrate and the adhesive layer at locations corresponding to the contact pads by way of a mechanical punching operation, with each of the vias having a via wall extending from the second surface of the electrically insulating substrate to a respective contact pad. At each via, the electrically insulating substrate comprises a protrusion extending outwardly from the first surface thereof so as to cover at least part of the adhesive layer in forming part of the via wall.Type: GrantFiled: June 9, 2022Date of Patent: November 21, 2023Assignee: General Electric CompanyInventors: Christopher James Kapusta, Youichi Nishihara
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Publication number: 20230273160Abstract: A system includes a sensor comprising a sensor bonding layer disposed on a surface of the sensor, wherein the sensor bonding layer is a metallic alloy. An inlay includes a planar outer surface, wherein the inlay may be disposed on a curved surface of a structure. A structure bonding layer may be disposed on the planar outer surface of the inlay, wherein the structure bonding layer is a metallic alloy. The sensor bonding layer is coupled to the structure bonding layer via a metallic joint, and the sensor is configured to sense data of the structure through the metallic joint, the structure bonding layer, and the sensor bonding layer. The inlay comprises at least one of a modulus of elasticity, a shape, a thickness, and a size configured to reduce strain transmitted to the sensor.Type: ApplicationFiled: April 14, 2023Publication date: August 31, 2023Applicant: General Electric CompanyInventors: Joseph Alfred Iannotti, Christopher James Kapusta, David Richard Esler
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Patent number: 11630086Abstract: A system includes a sensor comprising a sensor bonding layer disposed on a surface of the sensor, wherein the sensor bonding layer is a metallic alloy. An inlay includes a planar outer surface, wherein the inlay may be disposed on a curved surface of a structure. A structure bonding layer may be disposed on the planar outer surface of the inlay, wherein the structure bonding layer is a metallic alloy. The sensor bonding layer is coupled to the structure bonding layer via a metallic joint, and the sensor is configured to sense data of the structure through the metallic joint, the structure bonding layer, and the sensor bonding layer. The inlay comprises at least one of a modulus of elasticity, a shape, a thickness, and a size configured to reduce strain transmitted to the sensor.Type: GrantFiled: June 29, 2021Date of Patent: April 18, 2023Assignee: General Electric CompanyInventors: Joseph Alfred Iannotti, Christopher James Kapusta, David Richard Esler
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Publication number: 20230114057Abstract: The disclosure relates to an apparatus and method for liquid cooling of an electronic component. A housing includes an insertion slot and defines at least one component chamber for carrying the electronic component. A fluid inlet and fluid outlet are provided on the housing. A liquid coolant circuit passes through the housing at least from the inlet to the outlet.Type: ApplicationFiled: October 12, 2021Publication date: April 13, 2023Inventors: Brian Magann Rush, Christopher James Kapusta, David Richard Esler, Liang Yin, Richard Anthony Eddins, Judd Everett Swanson, Liqiang Yang
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Patent number: 11551993Abstract: A power overlay (POL) module includes a semiconductor device having a first side and an opposing second side, a dielectric sheet having a first side coupled to the semiconductor device second side, and an opposing second side, the dielectric sheet defining an aperture therethrough. The POL module also includes a first conductive layer disposed on the second side of the dielectric sheet and electrically coupled through the aperture to the semiconductor device second surface, a first conductive plate having a first side, and an opposing second side coupled to the first surface of the semiconductor device. The POL module further includes a first heat sink coupled the first side of the conductive plate and a first thermal interface layer disposed between the first conductive plate and the first heat sink.Type: GrantFiled: August 28, 2020Date of Patent: January 10, 2023Assignee: GE Aviation Systems LLCInventors: David Richard Esler, Christopher James Kapusta, Arun V. Gowda, Weijun Yin, Liqiang Yang, Richard Anthony Eddins
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Patent number: 11538769Abstract: A semiconductor device is provided. The semiconductor device includes an electric field (E-field) suppression layer formed over a termination region. The E-field suppression layer is patterned with openings over metal contact areas. The E-field suppression layer has a thickness such that an electric field strength above the E-field suppression layer is below a dielectric strength of an adjacent material when the semiconductor device is operating at or below a maximum voltage.Type: GrantFiled: December 14, 2018Date of Patent: December 27, 2022Assignee: General Electric CompanyInventors: Stephen Daley Arthur, Liangchun Yu, Nancy Cecelia Stoffel, David Richard Esler, Christopher James Kapusta
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Patent number: 11499545Abstract: A sensor system for monitoring a condition of a piston rod includes an interrogator system having a first coil winding coupled to a housing and radially spaced from the piston rod such that a gap is defined between the first coil winding and the piston rod. A second coil winding is coupled to the piston rod and is inductively coupled to the first coil winding. The second coil winding is configured to communicate with the first coil winding through a range of linear movement of the piston rod relative to the housing. A sensor is coupled to the second coil winding. The sensor is configured to measure a characteristic associated with the piston rod and generate a current in the second coil winding to transmit, via the inductive coupling with the first coil winding, an electrical output signal associated with the characteristic to the interrogator system.Type: GrantFiled: July 19, 2019Date of Patent: November 15, 2022Assignee: General Electric CompanyInventors: Joseph Alfred Iannotti, Christopher James Kapusta, Marco Francesco Aimi
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Patent number: 11503704Abstract: An electronics package is disclosed. The electronics package includes a first radio frequency (RF) substrate layer, a second RF substrate layer, and a plurality of conductive layers disposed adjacent to at least one of the first RF substrate layer and the second RF substrate layer and including an inner conductive layer disposed between and adjacent to both the first RF substrate layer and the second RF substrate layer. The inner conductive layer bonds the first RF substrate layer to the second RF substrate layer. The electronics package also includes a plurality of conductive interconnects extending through the first RF substrate layer and the second RF substrate layer and electrically coupled between at least two of the plurality of conductive layers.Type: GrantFiled: December 30, 2019Date of Patent: November 15, 2022Assignee: General Electric CompanyInventors: Christopher James Kapusta, Stanton Earl Weaver, Jr., Joseph Alfred Iannotti
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Publication number: 20220302063Abstract: An electronics package includes an electrically insulating substrate having a first surface and a second surface, an adhesive layer positioned on the first surface of the electrically insulating substrate, and an electrical component having a top surface coupled to the adhesive layer on a surface thereof opposite the electrically insulating substrate, the electrical component having contact pads on the top surface. Vias are formed through the electrically insulating substrate and the adhesive layer at locations corresponding to the contact pads by way of a mechanical punching operation, with each of the vias having a via wall extending from the second surface of the electrically insulating substrate to a respective contact pad. At each via, the electrically insulating substrate comprises a protrusion extending outwardly from the first surface thereof so as to cover at least part of the adhesive layer in forming part of the via wall.Type: ApplicationFiled: June 9, 2022Publication date: September 22, 2022Applicant: General Electric CompanyInventors: Christopher James Kapusta, Youichi Nishihara
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Patent number: 11398445Abstract: An electronics package includes an electrically insulating substrate having a first surface and a second surface, an adhesive layer positioned on the first surface of the electrically insulating substrate, and an electrical component having a top surface coupled to the adhesive layer on a surface thereof opposite the electrically insulating substrate, the electrical component having contact pads on the top surface. Vias are formed through the electrically insulating substrate and the adhesive layer at locations corresponding to the contact pads by way of a mechanical punching operation, with each of the vias having a via wall extending from the second surface of the electrically insulating substrate to a respective contact pad. At each via, the electrically insulating substrate comprises a protrusion extending outwardly from the first surface thereof so as to cover at least part of the adhesive layer in forming part of the via wall.Type: GrantFiled: May 29, 2020Date of Patent: July 26, 2022Assignee: General Electric CompanyInventors: Christopher James Kapusta, Youichi Nishihara
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Patent number: 11309304Abstract: An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween.Type: GrantFiled: April 18, 2018Date of Patent: April 19, 2022Assignee: General Electric CompanyInventors: James Sabatini, Christopher James Kapusta, Glenn Forman
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Publication number: 20220070996Abstract: A power overlay (POL) module includes a semiconductor device having a first side and an opposing second side, a dielectric sheet having a first side coupled to the semiconductor device second side, and an opposing second side, the dielectric sheet defining an aperture therethrough. The POL module also includes a first conductive layer disposed on the second side of the dielectric sheet and electrically coupled through the aperture to the semiconductor device second surface, a first conductive plate having a first side, and an opposing second side coupled to the first surface of the semiconductor device. The POL module further includes a first heat sink coupled the first side of the conductive plate and a first thermal interface layer disposed between the first conductive plate and the first heat sink.Type: ApplicationFiled: August 28, 2020Publication date: March 3, 2022Inventors: David Richard Esler, Christopher James Kapusta, Arun V. Gowda, Weijun Yin, Liqiang Yang, Richard Anthony Eddins
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Publication number: 20210375813Abstract: An electronics package includes an electrically insulating substrate having a first surface and a second surface, an adhesive layer positioned on the first surface of the electrically insulating substrate, and an electrical component having a top surface coupled to the adhesive layer on a surface thereof opposite the electrically insulating substrate, the electrical component having contact pads on the top surface. Vias are formed through the electrically insulating substrate and the adhesive layer at locations corresponding to the contact pads by way of a mechanical punching operation, with each of the vias having a via wall extending from the second surface of the electrically insulating substrate to a respective contact pad. At each via, the electrically insulating substrate comprises a protrusion extending outwardly from the first surface thereof so as to cover at least part of the adhesive layer in forming part of the via wall.Type: ApplicationFiled: May 29, 2020Publication date: December 2, 2021Applicant: General Electric CompanyInventors: Christopher James Kapusta, Youichi Nishihara
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Publication number: 20210325348Abstract: A system includes a sensor comprising a sensor bonding layer disposed on a surface of the sensor, wherein the sensor bonding layer is a metallic alloy. An inlay includes a planar outer surface, wherein the inlay may be disposed on a curved surface of a structure. A structure bonding layer may be disposed on the planar outer surface of the inlay, wherein the structure bonding layer is a metallic alloy. The sensor bonding layer is coupled to the structure bonding layer via a metallic joint, and the sensor is configured to sense data of the structure through the metallic joint, the structure bonding layer, and the sensor bonding layer. The inlay comprises at least one of a modulus of elasticity, a shape, a thickness, and a size configured to reduce strain transmitted to the sensor.Type: ApplicationFiled: June 29, 2021Publication date: October 21, 2021Applicant: General Electric CompanyInventors: Joseph Alfred Iannotti, Christopher James Kapusta, David Richard Esler
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Patent number: 11079359Abstract: A system includes a structure bonding layer and a sensor. The structure bonding layer is disposed on a structure. The structure bonding layer is a metallic alloy. The sensor includes a non-metallic wafer and a sensor bonding layer disposed on a surface of the non-metallic wafer. The sensor bonding layer is a metallic alloy. The sensor bonding layer is coupled to the structure bonding layer via a metallic joint, and the sensor is configured to sense data of the structure through the metallic joint, the structure bonding layer, and the sensor bonding layer.Type: GrantFiled: December 19, 2019Date of Patent: August 3, 2021Assignee: General Electric CompanyInventors: Joseph Alfred Iannotti, Christopher James Kapusta, David Richard Esler
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Publication number: 20210204397Abstract: An electronics package is disclosed. The electronics package includes a first radio frequency (RF) substrate layer, a second RF substrate layer, and a plurality of conductive layers disposed adjacent to at least one of the first RF substrate layer and the second RF substrate layer and including an inner conductive layer disposed between and adjacent to both the first RF substrate layer and the second RF substrate layer. The inner conductive layer bonds the first RF substrate layer to the second RF substrate layer. The electronics package also includes a plurality of conductive interconnects extending through the first RF substrate layer and the second RF substrate layer and electrically coupled between at least two of the plurality of conductive layers.Type: ApplicationFiled: December 30, 2019Publication date: July 1, 2021Inventors: Christopher James Kapusta, Stanton Earl Weaver, JR., Joseph Alfred Iannotti
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Publication number: 20210104812Abstract: A wireless access point is disclosed. The wireless access point includes a substrate, an antenna structure disposed on the substrate and configured to transmit and receive wireless electromagnetic communication signals, and a fiber-optic interface disposed on the substrate and communicatively coupled to the antenna structure and a fiber-optic cable. The fiber-optic interface is configured to transmit and receive optical communication signals through the fiber-optic cable.Type: ApplicationFiled: December 13, 2019Publication date: April 8, 2021Inventors: Christopher James Kapusta, Joseph Alfred Iannotti, Stanton Earl Weaver, Glen Peter Koste
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Patent number: 10957832Abstract: A light emitting semiconductor (LES) device having desirable thermal performance characteristics is disclosed. The LES device includes an insulating substrate layer having a plurality of vias formed therein and at least one LES chip mounted on the insulating substrate layer, with each of the LES chips(s) including an active surface including a light emitting area configured to emit light therefrom and a back surface positioned on a top surface of the insulating substrate layer and including connection pads thereon. A conductor layer is positioned on a bottom surface of the insulating substrate layer and in the vias, the conductor layer in direct contact with the connection pads of the LES chip(s) so as to be electrically and thermally connected thereto. An encapsulant is positioned adjacent the top surface of the insulating substrate layer and surrounding at least part of the LES chip(s), the encapsulant comprising a light transmitting material.Type: GrantFiled: October 22, 2018Date of Patent: March 23, 2021Assignee: General Electric CompanyInventors: Christopher James Kapusta, Risto Ilkka Sakari Tuominen, Kaustubh Ravindra Nagarkar