Patents by Inventor Chuan-Cheng Cheng
Chuan-Cheng Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8921938Abstract: Some of the embodiments of the present disclosure provide a transistor comprising a p-type well; and an n-type well; wherein at least a part of one of the p-type well and the n-type well overlaps with at least a part of another of the p-type well and the n-type well. Other embodiments are also described and claimed.Type: GrantFiled: February 13, 2013Date of Patent: December 30, 2014Assignee: Marvell International Ltd.Inventors: Xin Yi Zhang, Weidan Li, Chuan-Cheng Cheng, Jian-Hung Lee, Chung Chyung (Jason) Han
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Patent number: 8861214Abstract: Substrates for integrated passive devices are described herein. Embodiments of the present invention provide substrates including a glass layer and at least one passive device disposed thereon. According to various embodiments of the present invention, the glass layer may have a thickness adapted to minimize conductive and/or other interactions between the substrate and the at least one passive device. Other embodiments may be described and claimed.Type: GrantFiled: October 31, 2007Date of Patent: October 14, 2014Assignee: Marvell International Ltd.Inventors: Albert Wu, Chuan-Cheng Cheng
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Patent number: 8753960Abstract: A semiconductor wafer including an electrostatic discharge (ESD) protective device, and methods for fabricating the same. In one aspect, the method includes forming a first semiconductor device in a first semiconductor die region on the semiconductor wafer; forming a second semiconductor device in a second semiconductor die region on the semiconductor wafer; and forming a protective device in a scribe line region between (i) the first semiconductor die region and (ii) the second semiconductor die region.Type: GrantFiled: February 7, 2013Date of Patent: June 17, 2014Assignee: Marvell International Ltd.Inventors: Chuan-Cheng Cheng, Choy Hing Li, Shuhua Yu
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Publication number: 20140124961Abstract: Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed.Type: ApplicationFiled: January 13, 2014Publication date: May 8, 2014Applicant: Marvell World Trade Ltd.Inventors: Albert WU, Roawen Chen, Chung Chyung Han, Shiann-Ming Liou, Chien-Chuan Wei, Runzi Chang, Scott Wu, Chuan-Cheng Cheng
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Publication number: 20140103452Abstract: In an embodiment, an apparatus includes a substrate including a surface having a planar portion and a fin feature extending in a direction substantially perpendicular to the planar portion and having a thickness less than a thickness of the substrate. The apparatus also includes a first transistor that includes a first gate region formed over the fin feature, a first source region formed from a body of the fin feature, and a first drain region formed from the body of the fin feature. Additionally, the apparatus includes a second transistor that includes a second gate region formed over the fin feature, a second source region formed from the body of the fin feature, and a second drain region formed from the body of the fin feature. Further, the apparatus includes an isolation component formed between the first transistor and the second transistor, where the isolation component has a width less than 30 nm.Type: ApplicationFiled: October 10, 2013Publication date: April 17, 2014Applicant: Marvell World Trade Ltd.Inventors: Runzi Chang, Chuan-Cheng Cheng
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Patent number: 8372729Abstract: A semiconductor wafer including an electrostatic discharge (ESD) protective device, and methods for fabricating the same. In one aspect, the method includes forming a first semiconductor device in a first semiconductor die region on the semiconductor wafer; forming a second semiconductor device in a second semiconductor die region on the semiconductor wafer; and forming a protective device in a scribe line region between (i) the first semiconductor die region and (ii) the second semiconductor die region.Type: GrantFiled: October 31, 2011Date of Patent: February 12, 2013Assignee: Marvell International Ltd.Inventors: Chuan-Cheng Cheng, Choy Hing Li, Shuhua Yu
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Publication number: 20120098127Abstract: Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.Type: ApplicationFiled: October 19, 2011Publication date: April 26, 2012Inventors: Sehat Sutardja, Chung Chyung Han, Weidan Li, Shuhua Yu, Chuan-Cheng Cheng, Albert Wu
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Patent number: 8049249Abstract: A semiconductor wafer with an electrostatic discharge (ESD) protective device is disclosed. The semiconductor wafer includes first and second adjacent semiconductor die regions, a protective device in a scribe line region between the first and second die regions, and at least one metal line on a surface of the first die region, wherein the metal line(s) is/are in electrical communication with the protective device.Type: GrantFiled: September 14, 2006Date of Patent: November 1, 2011Assignee: Marvell International Ltd.Inventors: Chuan-Cheng Cheng, Choy Hing Li, Shuhua Yu
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Patent number: 8044733Abstract: Some of the embodiments of the present disclosure provide an apparatus comprising a voltage controlled oscillator (VCO) having a first transistor, a first resistor operatively coupled between a first terminal of the first transistor and a first node, a first capacitor operatively coupled between a second terminal of the first transistor and the first node, and a second capacitor operatively coupled to the first node, wherein the first capacitor and the second capacitor forms a capacitive voltage divider. Other embodiments are also described and claimed.Type: GrantFiled: August 3, 2009Date of Patent: October 25, 2011Assignee: Marvell International Ltd.Inventors: Himanshu Arora, Belal Helal, Chuan-Cheng Cheng
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Publication number: 20110186998Abstract: Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.Type: ApplicationFiled: January 24, 2011Publication date: August 4, 2011Inventors: Albert Wu, Roawen Chen, Chung Chyung Han, Shiann-Ming Liou, Chien-Chuan Wei, Runzi Chang, Scott Wu, Chuan-Cheng Cheng
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Publication number: 20110186960Abstract: Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed.Type: ApplicationFiled: January 14, 2011Publication date: August 4, 2011Inventors: Albert Wu, Roawen Chen, Chung Chyung Han, Shiann-Ming Liou, Chien-Chuan Wei, Runzi Chang, Scott Wu, Chuan-Cheng Cheng
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Publication number: 20110186992Abstract: Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.Type: ApplicationFiled: January 28, 2011Publication date: August 4, 2011Inventors: Albert Wu, Roawen Chen, Chung Chyung Han, Shiann-Ming Liou, Chien-Chuan Wei, Runzi Chang, Scott Wu, Chuan-Cheng Cheng
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Publication number: 20110175218Abstract: Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 20, 2010Publication date: July 21, 2011Inventors: Shiann-Ming Liou, Sehat Sutardja, Albert Wu, Chuan-Cheng Cheng, Chien-Chuan Wei
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Patent number: 7883947Abstract: Methods for fabricating and testing integrated circuit devices and systems. The integrated circuit device generally includes two semiconductor dies. The first die has little or no I/O or ESD protection, and the second die includes at least one exposed terminal in electrical communication with one or more terminals on the first die, at least one I/O circuit in electrical communication with one or more terminals on the second die, and at least one I/O terminal in electrical communication with the I/O circuit(s). The method of forming an integrated circuit includes aligning at least one of the exposed terminals on the first die with at least one of the exposed terminals on the second die, and forming at least one electrical junction between them such that the exposed terminal(s) on the first die is/are in electrical communication with an I/O circuit and an I/O terminal on the second die.Type: GrantFiled: August 17, 2010Date of Patent: February 8, 2011Assignee: Marvell International Ltd.Inventors: Chuan-Cheng Cheng, Choy Hing Li, Shiann-Ming Liou
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Patent number: 7820493Abstract: A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure.Type: GrantFiled: February 4, 2008Date of Patent: October 26, 2010Assignee: Marvell International Ltd.Inventors: Chuan-Cheng Cheng, Shuhua Yu, Roawen Chen, Albert Wu
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Patent number: 7808075Abstract: The integrated circuit devices disclosed herein generally include two semiconductor dies. The first die generally has little or no I/O or ESD protection and includes a first plurality of exposed terminals (e.g., bump pads). The second die generally includes (i) a second plurality of exposed terminals, wherein at least one of the second plurality of terminals is in electrical communication with one or more of the first plurality of terminals, (ii) a plurality of input and/or output (I/O) circuits, wherein at least one of the I/O circuits is in electrical communication with one or more of the second plurality of terminals, and (iii) a plurality of I/O terminals, wherein at least one of the I/O terminals is in electrical communication with one or more of the I/O circuits. The present invention advantageously provides the ability to fabricate the second die using different (e.g., less expensive) manufacturing processes than those used to fabricate the first die.Type: GrantFiled: August 16, 2006Date of Patent: October 5, 2010Assignee: Marvell International Ltd.Inventors: Chuan-Cheng Cheng, Choy Hing Li, Shiann-Ming Liou
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Patent number: 7704805Abstract: A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure.Type: GrantFiled: February 4, 2008Date of Patent: April 27, 2010Assignee: Marvell International Ltd.Inventors: Chuan-Cheng Cheng, Shuhua Yu, Roawen Chen, Albert Wu
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Patent number: 7589363Abstract: A structure configured to disconnect circuit elements. The structure generally includes a dielectric layer over a light-absorbing structure, and a lens over the dielectric layer and the light-absorbing structure, configured to at least partially focus light onto the light-absorbing structure. The light-absorbing structure absorbs a first wavelength of light with a minimum threshold efficiency, the lens is substantially opaque to the first wavelength of light, and the dielectric layer is substantially transparent to the first wavelength of light. The structure advantageously provides improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).Type: GrantFiled: May 22, 2007Date of Patent: September 15, 2009Assignee: Marvell International Ltd.Inventors: Chuan-Cheng Cheng, Shuhua Yu, Roawen Chen, Albert Wu
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Patent number: 7344924Abstract: A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure.Type: GrantFiled: May 24, 2005Date of Patent: March 18, 2008Assignee: Marvell International Ltd.Inventors: Chuan-Cheng Cheng, Shuhua Yu, Roawen Chen, Albert Wu
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Patent number: 6940107Abstract: A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure.Type: GrantFiled: December 12, 2003Date of Patent: September 6, 2005Assignee: Marvell International Ltd.Inventors: Chuan-Cheng Cheng, Shuhua Yu, Roawen Chen, Albert Wu