Abstract: An electrical connection device includes a mother board and a daughter board. The mother board includes a first board body with at least one cavity and a first electrical contact printed on the first board body. The daughter board includes a second board body and a second electrical contact printed on the second board body. At least one of the daughter board and the mother board includes at least one contour feature integrally formed with at least one of the first board body and the second board body. When the second board body is inserted into the at least one cavity of the first board body, the second electrical contact is electrically connected to the first electrical contact, and the daughter board is positioned in the mother board through the at least one contour feature.

Abstract: A method for tuning a plurality of image signal processor (ISP) parameters of a camera includes performing a first iteration. The first iteration includes extracting image features from an initial image, arranging a tuning order of the plurality of ISP parameters of the camera according to at least the plurality of ISP parameters and the image features, tuning a first set of the ISP parameters according to the tuning order to generate a first tuned set of the ISP parameters, and replacing the first set of the ISP parameters with the first tuned set of the ISP parameters in the plurality of ISP parameters to generate a plurality of updated ISP parameters.

Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.

Abstract: An isotopic polymer includes a silicone resin, an aromatic polymer, a modified silicone resin, a halogenated polysilane, an epoxy resin, or a combination thereof, wherein at least part of 12C, 1H and/or 16O in the isotopic polymer is replaced with 14C, 3H and/or 15O. The decaying age of the isotopic polymer is less than 50,000 years.

Abstract: A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.

Abstract: The invention discloses a method for inhibiting the growth of cancer cells by use of an anti-cancer composition containing a conditioned cell culture medium from mesenchymal stem cells and cytokines. It comprises the steps of applying a composition with a conditioned cell culture medium from stem cells and at least one cytokine to cancer cells for growth inhibition of the cancer cells. The cell culture medium can be conditioned with Wharton's Jelly mesenchymal stem cells (WJMSCs) as an WJMSCs-conditioned cell culture medium, and the at least one cytokine is selected from a group consisting of bone morphogenetic protein-4, Dickkopf-related protein, Interferon-? and tumor necrosis factor-related apoptosis-inducing ligand.

Abstract: A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.

Abstract: An electric frothing device includes a driving unit, a connecting rod, and a frothing unit. The driving unit has a housing, and a drive motor disposed in the housing. The drive motor has a power outputting shaft. The connecting rod is fixed to the power outputting shaft of the drive motor. The frothing unit has a fan fixed to the connecting rod and having blades, and a coil spring disposed with an interval from the blades of the fan.

Abstract: A sacrificial layer is formed over a first channel structure of an N-type transistor (NFET) and over a second channel structure of a P-type transistor (PFET). A PFET patterning process is performed at least in part by etching away the sacrificial layer in the PFET while protecting the NFET from being etched. After the PFET patterning process has been performed, a P-type work function (WF) metal layer is deposited in both the NFET and the PFET. An NFET patterning process is performed at least in part by etching away the P-type WF metal layer and the sacrificial layer in the NFET while protecting the PFET from being etched. After the NFET patterning process has been performed, an N-type WF metal layer is deposited in both the NFET and the PFET.

Abstract: A container assembly in accordance with one embodiment of the present disclosure includes an outer container having a first open end and a second closed end and defining an inner cavity; and a plunging assembly configured to be received within the outer container, the plunging assembly having a first end and a second end, wherein the plunging assembly includes an inner sleeve having a first end and a second end and a wall defining an inner bore, and wherein the plunging assembly includes an extraction assembly having a body having a first end and a second end and a side wall extending for at least a portion of the distance between the first and second ends of the body, wherein the first end of the body is coupled to the inner sleeve at or near the second end of the inner sleeve, and wherein the body includes a first sieve portion, and wherein the extraction assembly further includes a strainer having a second sieve portion, wherein the strainer is removably couplable to the body.

Abstract: The invention relates to a technical field of car roller shutter door production, in particular to a method for manufacturing a car roller shutter door. A single film piece is firstly vacuum formed into a desired shape, and then rubber is injected into the film piece after vacuum forming, so that the rubber and the film piece are integrally formed to form a single roller shutter strip, and then a required number of single roller shutter strips are placed and laminated on a flexible substrate in an integrated and orderly manner to form a car roller shutter door. Each of roller shutter strips is independent of each other and does not interfere or affect each other, which improves flexibility of the car roller shutter door. Compared with long strips of whole film sheet on the car roller shutter door in the prior art, each of film pieces of the present invention is independent of each other and does not have defect of easy fracture of the whole film sheet, which makes service life long.

Abstract: Disclosed herein is a process for producing a recombinant Candida cell, which involves genetically engineering a parent Candida cell using a Clustered Regularly Interspaced Short Palindromic Repeats (CRISPR)/CRISPR-associated (Cas)(CRISPR/Cas) system. A recombinant Candida cell obtained using the process and a method for producing D-lactic acid from a biomass using the recombinant Candida cell are also disclosed.

Abstract: The invention discloses a method for inhibiting the growth of cancer cells by use of an anti-cancer composition containing a conditioned cell culture medium from mesenchymal stem cells and cytokines. It comprises the steps of applying a composition with a conditioned cell culture medium from stem cells and at least one cytokine to cancer cells for growth inhibition of the cancer cells. The cell culture medium can be conditioned with Wharton's Jelly mesenchymal stem cells (WJMSCs) as an WJMSCs-conditoned cell culture medium, and the at least one cytokine is selected from a group consisting of bone morphogenetic protein-4, Dickkopf-related protein, Interferon-? and tumor necrosis factor-related apoptosis-inducing ligand.

Abstract: A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.

Abstract: A protection circuit, and related method, for an electronic device including a first power output interface and a second power output interface is disclosed. The protection circuit includes a first switch element, coupled between a first voltage source and the first power output interface. The detection circuit being operation to detect an output voltage value of the second power output interface to generate a detection result. The first switch element, according to the detection result, connects the first voltage source to the first power output interface to allow the first power output interface to output power to an external terminal, or disconnects the first voltage source from the first power output interface.

Abstract: A method includes providing a structure having a substrate and a channel layer over the substrate; forming a high-k gate dielectric layer over the channel layer; forming a work function metal layer over the high-k gate dielectric layer; forming a silicide layer over the work function metal layer; annealing the structure such that a first portion of the work function metal layer that interfaces with the high-k gate dielectric layer is doped with silicon elements from the silicide layer; removing the silicide layer; and forming a bulk metal layer over the work function metal layer.

Abstract: A protection circuit, and related method, for an electronic device including a first power output interface and a second power output interface is disclosed. The protection circuit includes a first switch element, coupled between a first voltage source and the first power output interface. The detection circuit being operation to detect an output voltage value of the second power output interface to generate a detection result. The first switch element, according to the detection result, connects the first voltage source to the first power output interface to allow the first power output interface to output power to an external terminal, or disconnects the first voltage source from the first power output interface.