Abstract: A method of fabricating a bottom electrode for a capacitor is described in which a dielectric layer is formed on a substrate already comprising an isolation layer, an etching stop layer and a landing pad. Bit line structures and spacers are further formed on the dielectric layer. A node contact window opening is formed in the dielectric layer, exposing the landing pad, and a conformal first conductive layer is formed on the substrate. After a specially patterned mask layer is formed and the exposed first conductive layer is removed, an extended portion is formed connecting to the conductive layer to complete the fabrication of the columnar bottom electrode for a capacitor.

Abstract: A method of fabricating a capacitor on a substrate. The method includes sequentially forming a first dielectric layer and an etching barrier layer on the substrate, the etching barrier layer and the first dielectric layer having an opening formed therein. A conductive layer is formed on the etching barrier layer and fills the opening. The conductive layer is patterned to form a raised region on the conductive layer. Isolation spacers and conductive spacers are alternately formed on sidewalls of the raised region. The isolation spacers and the conductive spacers are concentrically layered. The isolation spacers are used as masks to remove the conductive spacers and a portion of the patterned conductive layer. The etching barrier layer is used as an etch stop layer. The isolation spacers and a portion of the patterned conductive layer are removed. The remaining patterned conductive layer forms a storage electrode of the capacitor.

Abstract: A method of forming a dual cylindrical capacitor on a semiconductor substrate having at least a device isolation structure and a transistor thereon is provided, wherein the transistor includes at least a gate and a source/drain region. A first insulation layer and a second insulation layer are formed on the substrate. An opening comprising an lower part penetrating through the first insulation layer and an upper part penetrating through the second insulation layer is formed to expose the source/drain region. A conductive layer is formed on the second insulation layer to fill the lower part of the opening and to cover a surface of the upper part of the opening. A spacer is formed on a part of the conductive layer on a side wall of the larger opening. A conductive spacer is formed on the spacer. The spacer is removed.

Abstract: A method is provided for fabricating a data-storage capacitor for a DRAM device, which can help increase the capacitance of the resulted capacitor. By this method, a first insulating layer, a second insulating layer, and a third insulating layer are sequentially formed over the substrate. An opening is formed in the third insulating layer, and a contact hole is formed to expose a source/drain region in the substrate. Subsequently, a conductive layer is formed over the third insulating layer, which is electrically connected to the exposed source/drain region. Next, a fourth insulating layer is formed over the conductive layer. A surface part of the third and fourth insulating layers is removed until reaching a predefined depth to allow an upper part of the conductive layer to be exposed. Next, conductive sidewall spacers are formed on the exposed part of the conductive layer to increase the surface area of the conductive layer.

Abstract: A method for fabricating a cylinder capacitor of a DRAM cell that starts with forming a first oxide layer and then a doped first polysilicon layer on a substrate, patterning the first polysilicon layer to form a first opening that exposes the first oxide layer, forming a polysilicon spacer at the laterals of the first opening. Then, a portion of the first oxide layer is removed to expose the substrate by using the polysilicon spacer and the first polysilicon layer as a mask. A doped second polysilicon layer is formed on the first polysilicon layer and in the first opening. A portion of the second polysilicon layer is removed to form a second opening. A oxide spacer is formed on the laterals of the second opening, and is used as mask to remove a portion of the second polysilicon layer for forming a lower electrode. A dielectric layer and then a third polysilicon layer are formed on the lower electrode after the silicon oxide spacer is removed, wherein the third polysilicon is an upper electrode.

Abstract: The present invention relates to a method of forming a lower electrode of a capacitor on a DRAM cell in a semiconductor wafer for increasing a surface area of the lower electrode. It is achieved by forming a second dielectric layer on a first polysilicon layer which comprises a plurality of doped horizontal layers along a vertical direction. Because dopant densities of the doped horizontal layers alternate in a high and low sequence, when forming a second polysilicon layer on the second dielectric layer, the second polysilicon layer will have many hemispherical grains on the vertical side wall of the second dielectric layer. This will result in an increased surface area of the lower electrode.

Abstract: A method for forming a cylinder capacitor on a dynamic random access memory (DRAM) device is provided. The method includes sequentially forming a dielectric layer, an etching stop layer, and an insulating layer over a substrate, having a field effect transistor (FET). An opening is formed to expose a source region of the FET by patterning the dielectric layer, the etching stop layer, and the insulating layer. A conductive layer is formed on the insulating layer with the opening being filled. A concave oxide structure is formed on the conductive layer. A portion of the conductive layer other than the concave structure is removed. The concave structure is etched to form two oxide pillars on the conductive layer. Four conductive spacers are formed on each side of the oxide pillars with an electrical coupling with the conductive layer. The oxide pillar and the insulating layer are removed to expose the conductive spacers and a portion of the conductive layer.

Abstract: A method of forming landing pads for a bit line and a node contact is provided. First, a first dielectric layer is formed on a substrate having a transistor structure thereon. The first dielectric layer is defined and etched in a self-aligned process to form a contact opening to the substrate. A second dielectric layer is formed on the first dielectric layer and is etched back to form a spacer on the opening sidewall. Then, a conductive layer is formed on the first dielectric layer and fills the opening. A bit line is formed by partially removing the conductive layer through a photo-resist mask provided on the conductive layer, wherein the conductive layer filling the opening is left to form a landing pad.

Abstract: A semiconductor fabrication method is provided for fabricating an electrode structure for a cylindrical capacitor in integrated circuit, which can allow the resultant electrode structure to be formed substantially without having horn-like portions such that the leakage current in the capacitor can be minimized.

Abstract: A method of manufacturing a DRAM capacitor comprises the steps of providing a substrate having a word line, a source/drain region, a bit line and a first insulator layer. A hard mask layer and a second insulator layer are formed on the first insulator layer in sequence. Next, an opening is formed to expose a portion of the first insulator layer by patterning the second insulator layer and the hard mask layer. Thereafter, a spacer is formed on the side wall of the opening and a node contact hole is formed to expose a portion of the source/drain region in the first insulator layer. The second insulator layer is stripped to expose the hard mask layer and a conductive layer is formed over the hard mask layer and fills the node contact hole. A bottom electrode is formed by patterning the conductive layer and a dielectric layer and another conductive layer are formed over the bottom electrode in sequence.

Abstract: A method of fabricating a capacitor. Isolation layers and conductive layers are formed alternately on a dielectric layer on a substrate. The conductive layers and the isolation layers are patterned to form an opening to expose a conductive region of the substrate. A spacer is formed on the sidewall of the conductive layers and the isolation layers exposed by the opening. The spacer is used as a mask to form a contact hole. The conductive layer on the dielectric layer is used as an etching stop layer. The isolation layers and the conductive layers are patterned. A conductive layer is formed to cover the substrate to cover the isolation layers and the conductive layers and to fill the contact hole. A portion of the conductive layers is removed to expose the spacer. The spacer and isolation layers are removed to expose the storage electrode formed by the conductive layers. A dielectric film layer and a cell electrode are formed in sequence over the substrate.

Abstract: A method of manufacturing a DRAM capacitor utilizes spacers to form a self-aligned node contact, and thus is able to reduce the cross-sectional dimensions of the node contact. Moreover, the spacers are capable of protecting any portion of a bit line that may be exposed due to misalignment when contact opening is formed. Hence, short-circuiting of the device can be prevented. Furthermore, by shaping the lower electrode of the capacitor into a fork-shaped structure with four prongs, the surface area for capacitor coupling is increased, thus increasing the capacitance of the capacitor, as well.

Abstract: A method for manufacturing a DRAM capacitor is provided to form a lower electrode with a cylindrical profile by using a first stage and a second stage. The stages provide different etching rates in various situations. The invention uses the stages to allow the part of the second polysilicon layer between the capacitors to be completely etched and prevent the other part of the second polysilicon layer serving as a lower electrode from over-etching. The invention provides an easier process of forming a cylindrical capacitor with a larger surface.

Abstract: A method of forming a DRAM capacitor that utilizes cap layers and spacers to surround the gate and bit line so that the necessary contact openings in a DRAM can be formed in two self-aligned contact processing operations. The capacitor of the DRAM is fabricated by forming contact node and openings within an insulating layer above a substrate, and then forming a first conductive layer conformal to the surface profile of the substrate above the substrate structure. Next, spacers are formed on the sidewalls of the conductive layer, and then a second conductive layer is formed filling the spacer between the spacers and over the substrate structure. Thereafter, a portion of the first conductive layer and the second conductive layer is removed to expose the spacers and the insulating layer. Finally, the spacers and the insulating layer are removed to expose a lower electrode structure that comprises the first and the second conductive layers.

Abstract: A method of fabricating a dual trench capacitor with a horn region is provided. On a semiconductor substrate having at least a device isolation structure and a transistor thereon, wherein the transistor includes at least a gate and a source/drain region, an insulation layer with an opening exposing the source/drain region is formed. The opening is partly filled with a conductive plug, the plug having a surface level lower than a surface level of the insulation layer, so that a trench with a side wall of the insulation layer is formed on the plug within the opening. A conductive spacer is formed on the side wall with a horn shape. A part of the insulation layer which encompassing the conductive plug and the conductive spacer is removed, so that a dual trench structure which exposes outer side walls of the conductive spacer and the conductive plug, and a part of the insulation layer is formed.

Abstract: A fabricating method for a dynamic random access memory capacitor includes the following steps. A cap layer and a spacer are formed on the gate to protect the gate from being etched. A self-aligned contact hole is formed and then the self-aligned contact hole is etched again to form a contact node opening. In this way, the difficulty of forming the contact node opening can be reduced. The method of forming the storage electrode includes forming and patterning a stacked layer, which is formed by several conductive layers and isolation layers interlaced with each other, to form the self-aligned contact hole. A conductive spacer is formed on the sidewall of the stacked layer. The conductive spacer is used as a mask to etch the dielectric layer below the bit line so as to form a contact node opening. The contact opening exposes a source/drain region. A conductive layer is formed to fill the contact node opening. The conductive layer and the staked layer are patterned.

Abstract: A method of improving the planarization of inter-poly dielectric layers. On a semiconductor device on which a poly-silicon layer is formed, by using atmosphere chemical vapor deposition, an undoped inter-poly dielectric layer is formed. A doped inter-poly dielectric layer is formed on the undoped inter-poly dielectric layer. Under a high temperature, reflow and etching back operations are performed for the doped inter-poly dielectric layer. Before a second poly-silicon layer is formed, a rapid thermal process is performed.

Abstract: A method of fabricating a capacitor structure for a dynamic random access memory. This method comprises the following steps: a transistor is provided on a semiconductor substrate, and spacers are formed over the sidewalls of a gate electrode of the transistor. A first oxide layer is formed over the transistor. A bit line is deposited to contact with the source region of the transistor. Thereafter, a second oxide layer is formed over the bit line. A contact opening is formed exposing the drain region. Then the hemispherical grained silicon layer is formed into the contact opening. A polysilicon layer is formed over the hemispherical grained silicon layer. Therefore both the hemispherical grained silicon layer and the third polysilicon layer have rough surfaces. Subsequent conventional processes for the complete formation of capacitor structure are performed. It is therefore the capacitor maintains a required capacitance while reducing the horizontal dimensions of the storage capacitor.

Abstract: A structure of a capacitor in a DRAM includes: A dielectric layer with a contact window for later connecting use is formed on a substrate. Then, a first-conductive layer is formed over the dielectric and is coupled to either the source or the drain of a TFET through the contact window. Subsequently, a number of insulating layers and second-conductive layers are superposed alternatively together to form a stacked layer. By using the space occupied by the insulating layers, a number of third-conductive layers replacing the inner portion of the insulating layers are formed in between the second-conductive layers. After removing the insulating layers between the second-conductive layers, a structure of a horn-like in a sectional view is formed. The first-conductive layer, the second-conductive layers and the third-conductive layers are coupled together to act as a lower electrode of the capacitor. Then, a dielectric thin film is formed over the lower electrode.