Patents by Inventor Chuan Shih

Chuan Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250254916
    Abstract: A method for manufacturing a semiconductor device includes: forming a channel including a semiconductor material; forming two intermediate conductive layers in contact with the channel and spaced apart from each other; and forming two conductive contacts respectively on the two intermediate conductive layers. Each of the intermediate conductive layers includes at least one stacking unit. The at least one stacking unit includes two first metal oxide layers spaced apart from each other and a second metal oxide layer disposed between the two first metal oxide layers and extending along a lengthwise line such that the two first metal oxide layers are opposite to each other relative to the lengthwise line. Each of the first metal oxide layers includes first metal atoms. The second metal oxide layer includes second metal atoms that are different from the first metal atoms.
    Type: Application
    Filed: February 7, 2024
    Publication date: August 7, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Chieh HUANG, Huai-Ying HUANG, Yu-Chuan SHIH, Chun-Chieh LU, I-Che LEE, Yu-Ming LIN
  • Publication number: 20250248046
    Abstract: A semiconductor device includes a first electrode layer, a ferroelectric layer and a first alignment layer. The first alignment layer is disposed between the first electrode layer and the ferroelectric layer, and the ferroelectric layer and the first alignment layer have the same crystal lattice orientation. In some embodiments, a material of the first alignment layer has a band gap smaller than 50 meV.
    Type: Application
    Filed: March 20, 2025
    Publication date: July 31, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lu, Qing Shi, Bo-Feng Young, Yu-Chuan Shih, Sai-Hooi Yeong, Blanka Magyari-Kope, Ying-Chih Chen, Tzer-Min Shen, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 12376347
    Abstract: Provided are a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes: a gate electrode; a ferroelectric layer, disposed on the gate electrode; a channel layer, disposed on the ferroelectric layer; a pair of source/drain (S/D) electrodes, disposed on the channel layer; a first insertion layer, disposed between the gate electrode and the ferroelectric layer; and a second insertion layer, disposed between the ferroelectric layer and the channel layer, wherein the second insertion layer has a thickness less than a thickness of the first insertion layer.
    Type: Grant
    Filed: August 12, 2022
    Date of Patent: July 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chang Chiang, Yu-Chuan Shih, Chun-Chieh Lu, Po-Ting Lin, Hai-Ching Chen, Sai-Hooi Yeong, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20250241015
    Abstract: Oxide semiconductor ferroelectric field effect transistors (OS-FeFETs) and method of forming the same are provide. A device disclosed herein includes an electrode in a first dielectric layer, a ferroelectric layer over the electrode and the first dielectric layer, a high-k dielectric layer over the ferroelectric layer, an oxide semiconductor layer over the high-k dielectric layer, a second dielectric layer over the oxide semiconductor layer and the high-k dielectric layer, and a first contact feature and a second contact feature extending through the second dielectric layer to contact the oxide semiconductor layer.
    Type: Application
    Filed: March 28, 2024
    Publication date: July 24, 2025
    Inventors: Chun-Chieh Lu, Yu-Chuan Shih, Yu-Ming Lin
  • Publication number: 20250227934
    Abstract: A method is provided. The method includes applying a first pulse to a ferroelectric memory device, measuring a memory window metric of the ferroelectric memory device, and applying a second pulse to the ferroelectric memory device. The first pulse may have a first voltage magnitude. The second pulse may have a second voltage magnitude. The second voltage magnitude may be determined based at least in part on the measured memory window metric.
    Type: Application
    Filed: January 8, 2024
    Publication date: July 10, 2025
    Inventors: YU-CHUAN SHIH, YU-KAI CHANG, PEI-CHUN LIAO, HUAI-YING HUANG, CHUN-CHIEH LU, YU-MING LIN
  • Publication number: 20250212417
    Abstract: A semiconductor structure includes a gate layer, a ferroelectric layer, a source structure, a drain structure, an oxide semiconductor and a high-k material layer. The gate layer is disposed in an interconnect structure. The ferroelectric layer is disposed over the gate layer. The source structure and the drain structure are disposed over the ferroelectric layer. The oxide semiconductor is disposed over the ferroelectric layer and between the source structure and the drain structure. The high-k material layer is disposed on and contacts a surface of the ferroelectric layer. A method of manufacturing the semiconductor structure is also provided.
    Type: Application
    Filed: December 25, 2023
    Publication date: June 26, 2025
    Inventors: YU-CHUAN SHIH, CHUN-CHIEH LU, KUO-CHANG CHIANG, CHIH-YU CHANG, HUAI-YING HUANG, YU-MING LIN
  • Publication number: 20250204928
    Abstract: A pressurized tourniquet includes an elastic band, a hemostatic dressing, and a pressurized member. A through tough is formed at the outer surface of the elastic band and has an extending direction vertical to the longitudinal direction of the elastic band and parallel to the width direction of the elastic band. The hemostatic dressing is disposed to the inner surface of the elastic band. The pressurized member has a base portion, an insertion portion connected with the base portion and detachably inserted in the through tough and having one end forming an anchor portion protruding from and interfered with the through tough, and a pressurized portion connected with the base portion and parallel to the insertion portion to form a slot therebetween for passage of the elastic band. Thus, the pressurized tourniquet of the present invention has advantages of convenient manufacturing and easy replacement of accessories.
    Type: Application
    Filed: February 6, 2024
    Publication date: June 26, 2025
    Applicants: SOLID YEAR CO., LTD., TAICEND TECHNOLOGY CO., LTD.
    Inventors: Yu-Ren LIOU, Chao-Hsin LIN, Chuan-Shih WU, Gou-Don CHU
  • Publication number: 20250202335
    Abstract: A power conversion circuit including a first input circuit, a second input circuit, a linear regulator, a switch, and a switch control circuit is provided. The first input circuit receives a first input voltage through a first input terminal. The second input circuit receives a second input voltage through a second input terminal. The first input voltage is higher than the second input voltage. The linear regulator receives the first or the second input voltage to generate an output voltage. The switch has a first terminal coupled to the first input circuit and a second terminal coupled to the second input circuit and the linear regulator. The switch control circuit outputs a control signal to open the switch after receiving the second input voltage that has reached a predetermined level, so that the linear regulator generates the output voltage according to the second input voltage.
    Type: Application
    Filed: April 26, 2024
    Publication date: June 19, 2025
    Inventors: Yu-Chuan SHIH, Hsin-Chih KUO
  • Publication number: 20250169118
    Abstract: The current disclosure describes a new vertical tunnel field-effect transistor (TFET). The TFET includes a source layer over a substrate. A first channel layer is formed over the source layer. A drain layer is stacked over the first channel layer with a second channel layer stacked therebetween. The drain layer and the second channel layer overlap a first surface portion of the first channel layer. A gate structure is positioned over the channel layer by a second surface portion of the channel layer and contacts a sidewall of the second channel layer.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 22, 2025
    Inventors: Jiun-Yun Li, Pao-chuan Shih, Wei-Chih Hou
  • Patent number: 12289893
    Abstract: A semiconductor device includes a first electrode layer, a ferroelectric layer, a first alignment layer and a second electrode layer. A material of the first alignment layer includes rare-earth metal oxide. The ferroelectric layer and the first alignment layer are disposed between the first electrode layer and the second electrode layer, and the first alignment layer is disposed between the ferroelectric layer and the first electrode layer.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: April 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lu, Qing Shi, Bo-Feng Young, Yu-Chuan Shih, Sai-Hooi Yeong, Blanka Magyari-Kope, Ying-Chih Chen, Tzer-Min Shen, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20250121078
    Abstract: Disclosed are compounds of formula (I): in which L1, L2, LD1, LD2, R5, and R6 are defined. Also provided are pharmaceutical compositions containing such a compound a method of treating cancer using the compound.
    Type: Application
    Filed: October 4, 2024
    Publication date: April 17, 2025
    Inventors: Lun Kelvin Tsou, Yu-Wei Liu, Chiung-Tong Chen, Tai-Yu Chiu, Chuan Shih, Jang-Yang Chang
  • Publication number: 20250125012
    Abstract: A tumor neoantigen prediction method and a tumor neoantigen prediction system are provided. In the method, multiple amino acid sequences in genes of a person to be tested are extracted as multiple test peptides to be compared with multiple human protein sequences in a protein sequence database to find multiple similar peptides that match the human protein sequences. The similar peptides are filtered out from the test peptides and the filtered test peptides are input to multiple trained human leukocyte antigen (HLA) models to obtain multiple ranking results of the test peptides. A weighted sum of rankings of each test peptide in the ranking results is calculated as a score of the test peptide. At least one of the test peptides is selected as a neoantigen adapted for the person to be tested according to the score.
    Type: Application
    Filed: November 7, 2023
    Publication date: April 17, 2025
    Applicant: Acer Incorporated
    Inventors: Chi-Wei Lu, Ying-Ja Chen, Li-Tzu Yeh, Tao-Chuan Shih, Cing-Han Yang, Tun-Wen Pai
  • Publication number: 20250075019
    Abstract: A method for manufacturing a nitrile butadiene rubber includes: subjecting a material composition containing water, butadiene, acrylonitrile, an emulsifying agent, an initiator, and a molecular weight regulator to an emulsion polymerization reaction, so as to form an emulsion; and adding a reactive antioxidant and a non-reactive antioxidant to the emulsion to form a mixture, followed by subjecting the mixture to a coagulation process, so as to form the nitrile butadiene rubber.
    Type: Application
    Filed: December 11, 2023
    Publication date: March 6, 2025
    Inventors: Chun-Chuan SHIH, Yen-Ju CHEN, Hung-Yu CHEN, Pen-Hsin CHOU
  • Patent number: 12240858
    Abstract: Disclosed herein is a specific crystalline forms of (S, E)-4-(dimethylamino)-N-(3-(4-(2-hydroxy-1-phenylethylamino)-6-phenylfuro[2,3-d]pyrimidin-5-yl)phenyl)but-2-enamide (ABT-101) free base, the pharmaceutical composition and capsule comprising the same, and the medical application thereof. Said crystalline forms of ABT-101 free base can exhibit unexpected stability and improved pharmacokinetic properties compared to other forms or salt thereof, thereby allowing said compound more suitable for drug development and satisfying the requirements for bioavailability and drug efficacy.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: March 4, 2025
    Assignee: ANBOGEN THERAPEUTICS, INC
    Inventor: Chuan Shih
  • Patent number: 12237376
    Abstract: The current disclosure describes a new vertical tunnel field-effect transistor (TFET). The TFET includes a source layer over a substrate. A first channel layer is formed over the source layer. A drain layer is stacked over the first channel layer with a second channel layer stacked therebetween. The drain layer and the second channel layer overlap a first surface portion of the first channel layer. A gate structure is positioned over the channel layer by a second surface portion of the channel layer and contacts a sidewall of the second channel layer.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: February 25, 2025
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventors: Jiun-Yun Li, Pao-chuan Shih, Wei-Chih Hou
  • Publication number: 20250014945
    Abstract: A device structure can be formed by forming a layer stack comprising a continuous bottom electrode material layer, a continuous dielectric layer, and a continuous dielectric metal oxide layer; increasing an oxygen-to-metal ratio in a top surface portion of the continuous dielectric metal oxide layer by incorporating oxygen atoms into the top surface portion of the continuous dielectric metal oxide layer; depositing a continuous semiconductor layer over the continuous dielectric metal oxide layer; and patterning the continuous semiconductor layer and the layer stack to form a patterned layer stack including a bottom electrode, a dielectric layer, a dielectric metal oxide layer, and a semiconductor layer.
    Type: Application
    Filed: July 5, 2023
    Publication date: January 9, 2025
    Inventors: Yen-Chieh Huang, Huai-Ying Huang, Wei-Gang Chiu, Yu-Chuan Shih, Chun-Chieh Lu, Yu-Ming Lin
  • Publication number: 20240431116
    Abstract: The present disclosure relates a ferroelectric field-effect transistor (FeFET) device. The FeFET device includes a ferroelectric structure having a first side and a second side. A gate structure is disposed along the first side of the ferroelectric structure, and an oxide semiconductor is disposed along the second side of the ferroelectric structure. The oxide semiconductor has a first semiconductor type. A source region and a drain region are disposed on the oxide semiconductor. The gate structure is laterally between the source region and the drain region. A polarization enhancement structure is arranged on the oxide semiconductor between the source region and the drain region. The polarization enhancement structure includes a semiconductor material or an oxide semiconductor material having a second semiconductor type that is different than the first semiconductor type.
    Type: Application
    Filed: June 21, 2023
    Publication date: December 26, 2024
    Inventors: Kuo-Chang Chiang, Chung-Te Lin, Yu-Ming Lin, Po-Ting Lin, Yu-Chuan Shih
  • Publication number: 20240397725
    Abstract: A field-effect transistor (FET), selectively switchable between first and second states, includes: source and drain regions and a channel region disposed therebetween; a gate arranged to selectively receive a bias voltage which switches the FET between the first and second states; a memory structure between the gate and the channel region, structure including a first portion which is anti-ferroelectric and a second portion which is ferroelectric, both portions being polarized in a first direction when the FET is in the first state; and a depolarization dielectric layer disposed proximate to the memory structure. When the FET is set to the first state, the depolarization dielectric layer destabilizes a polarization of the second portion of the memory structure while maintaining a polarization of the first portion.
    Type: Application
    Filed: May 26, 2023
    Publication date: November 28, 2024
    Inventors: Chun-Chieh Lu, Yu-Ming Lin, Kuo-Chang Chiang, Yu-Chuan Shih, Huai-Ying Huang
  • Publication number: 20240381659
    Abstract: A semiconductor memory structure includes a gate structure, a ferroelectric layer over the gate structure, a channel layer over the ferroelectric layer, an intervening structure between the ferroelectric layer and the channel layer, and a source structure and a drain structure separated from each other over the channel layer. A thickness of the intervening structure is less than a thickness of the channel layer and less than a thickness of the ferroelectric layer. The channel layer and the intervening structure include different materials.
    Type: Application
    Filed: May 9, 2023
    Publication date: November 14, 2024
    Inventors: PO-TING LIN, CHUNG-TE LIN, HAI-CHING CHEN, YU-MING LIN, KUO-CHANG CHIANG, YAN-YI CHEN, WU-WEI TSAI, YU-CHUAN SHIH
  • Publication number: 20240368175
    Abstract: Disclosed herein is a specific crystalline forms of (S, E)-4-(dimethylamino)-N-(3-(4-(2-hydroxy-1-phenylethylamino)-6-phenylfuro[2,3-d]pyrimidin-5-yl)phenyl)but-2-enamide (ABT-101) free base, the pharmaceutical composition and capsule comprising the same, and the medical application thereof. Said crystalline forms of ABT-101 free base can exhibit unexpected stability and improved pharmacokinetic properties compared to other forms or salt thereof, thereby allowing said compound more suitable for drug development and satisfying the requirements for bioavailability and drug efficacy.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventor: Chuan Shih