Abstract: A training device includes a force receiving component, a location detector, a resistance generator, and a controller. The force receiving component moves along a closed trajectory. The location detector is configured to detect a location of the force receiving component in the closed trajectory and to output a location signal. The resistance generator is configured to exert a resistance on the force receiving component. The controller controls the resistance generator to adjust the resistance based on the location signal.

Abstract: The present application provides constructs comprising a single-domain antibody (sdAb) moiety that specifically recognizes TIGIT. Also provided are methods of making and using these constructs.

Abstract: The present application provides anti-LAG-3 constructs comprising a single-domain antibody (sdAb) that specifically recognizes LAG-3. Also provided are methods of making and using these constructs.

Abstract: A fan-out semiconductor device includes stacked semiconductor dies having die bond pads arranged in columns exposed at a sidewall of the stacked semiconductor dies. The stacked dies are encapsulated in a photo imageable dielectric (PID) material, which is developed to form through-hole cavities that expose the columns of bond pads of each die at the sidewall. The through-hole cavities are plated or filled with an electrical conductor to form conductive through-holes coupling die bond pads within the columns to each other.

Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. The conductive ring-like structure surrounds a central region of the chip. The chip package structure includes a first solder structure over the conductive ring-like structure. The first solder structure and the conductive ring-like structure are made of different materials.

Abstract: Positive reference spiked in collected sample for use in qualitatively and quantitatively detecting viral RNA.

Abstract: A method includes receiving a structure that includes a substrate including a first well region having a first dopant type and a second well region having a second dopant type that is opposite to the first dopant type; and fins extending above the substrate. The method further includes forming a patterned etch mask on the structure, wherein the patterned etch mask provides an opening that is directly above a first fin of the fins, wherein the first fin is directly above the first well region. The method further includes etching the structure through the patterned etch mask, wherein the etching removes the first fin and forms a recess in the substrate that spans from the first well region into the second well region; and forming a dielectric material between remaining portions of the fins and within the recess.

Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.

Abstract: A memory device having a switching device for a page buffer is provided, and includes a plurality of switching units coupled between a memory cell array and a sense amplification circuit of the page buffer. Each of the plurality of switching units further comprising: a high voltage element and a low voltage element that are connected in series to each other. A first end of the high voltage element is coupled to the sense amplification circuit, and a first end of the low voltage element is coupled to a common source line of the memory cell array. A second end of the high voltage element and a second end of the low voltage element are connected to each other and coupled to a corresponding bit line of the memory cell array. The common source line coupled to each of the plurality of switching units shares a common active region.

Abstract: Provided is a production method of a high-rate lithium iron phosphate positive electrode material comprising first, weighing an iron source and a lithium source in a molar ratio of 1:1-1:1.05, then weighing 5-15% of carbon source and 0-1% of metal ion doping agent based on the total mass of the iron source and lithium source, adding water to the above weighed materials, ball milling and sand grinding the obtained slurry, so that the D50 after the sand grinding is controlled to be 100-200 nm, then spraying the mixture to obtain a precursor, putting the precursor into a sintering furnace for sintering at 650-700° C. under the protection of nitrogen gas, cooling to obtain a sintered material, then pulverizing the sintered material, sieving the pulverized material and removing iron to obtain the lithium iron phosphate. The prepared lithium iron phosphate has a good rate capability and a good cycle stability.

Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.

Abstract: A method of forming a semiconductor device includes providing a substrate including a circuit region and a well strap region, forming a mandrel extending from the circuit region to the well strap region, depositing mandrel spacers on sidewalls of the mandrel, removing the mandrel in the circuit region, while the mandrel in the well strap region remains intact, patterning the substrate with the mandrel spacers in the circuit region and the mandrel in the well strap region as an etch mask, thereby forming at least a first fin in the circuit region and a second fin in the well strap region, and epitaxially growing a first epitaxial feature over the first fin in the circuit region and a second epitaxial feature over the second fin in the well strap region. A width of the second fin is larger than a width of the first fin.

Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.

Abstract: A car safety device for pets includes a fixing frame mounted in a seat cushion and a seat cushion cover. The seat cushion with the fixing frame is placed into the seat cushion cover and one end of a support rod of the fixing frame is protruding from the seat cushion cover. While in use, the device is placed on a car seat and an anchor member on the support rod of the fixing frame is connected to a support bar of the car seat. Then a pet carrier bag is disposed on the seat cushion cover and a second connecting member of the pet carrier bag is connected with a first connecting member on the seat cushion cover to fix the pet carrier bag on the present device. Thereby the pet carrier bag is firmly mounted on the car seat and pet safety is improved.

Abstract: A positioning system and a positioning method based on radio frequency identification techniques (RFID) are provided. The positioning system includes in-vehicle devices, RFID readers and a server. The in-vehicle devices each includes a positioning device, an image capturing device and an image recognition module. The positioning device obtains a positioning location. The image capturing device captures a driving image. The image recognition module identifies adjacent vehicles, adjacent license plate information, and road attributes, and calculates relative location information. Each of the RFID readers reads a vehicle tag of one of the vehicles passing by, so as to mark a reference vehicle and generate reference vehicle information. A positioning adjustment module of the server determines whether the target vehicle is a reference vehicle, has been the reference vehicle or is a non-reference vehicle, and adjusts the positioning location of the target vehicle in different ways, accordingly.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) having a device section and a pick-up section. The IC includes a semiconductor substrate. A first fin of the semiconductor substrate is disposed in the device section. A second fin of the semiconductor substrate is disposed in the pick-up section and laterally spaced from the first fin in a first direction. A gate structure is disposed in the device section and laterally spaced from the second fin in the first direction. The gate structure extends laterally over the semiconductor substrate and the first fin in a second direction perpendicular to the first direction. A pick-up region is disposed on the second fin. The pick-up region continuously extends from a first sidewall of the second fin to a second sidewall of the second fin. The first sidewall is laterally spaced from the second sidewall in the first direction.

Abstract: Well pick-up (WPU) regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region, a WPU region, a first well extending lengthwise along a first direction through the circuit region and into the WPU region, a second well extending lengthwise along the first direction through the circuit region and into the WPU region, and a third well physically connecting a portion of the first well in the WPU region and a portion of the second well in the WPU region.

Abstract: Methods and devices that provide a first fin structure, a second fin structure, and a third fin structure disposed over a substrate. A dielectric fin is formed between the first fin structure and the second fin structure, and a conductive line is formed between the second fin structure and the third fin structure.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a stack structure including interleaved conductive layers and dielectric layers and having a core array region and a staircase region in a plan view, one or more channel structures each extending through the core array region of the stack structure, and one or more contact structures each extending through the stack structure, wherein each of the one or more contact structures includes a head portion and a body portion, and a width of the head portion of the respective contact structure is larger than that of the body portion of the respective contact structure.

Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.