Patents by Inventor Chuan Yang

Chuan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12191306
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming an epitaxial structure having a first doping type over a first portion of a semiconductor substrate. A second portion of the semiconductor substrate is formed over the epitaxial structure and the first portion of the semiconductor substrate. A first doped region having the first doping type is formed in the second portion of the semiconductor substrate and directly over the epitaxial structure. A second doped region having a second doping type opposite the first doping type is formed in the second portion of the semiconductor substrate, where the second doped region is formed on a side of the epitaxial structure. A plurality of fins of the semiconductor substrate are formed by selectively removing portions of the second portion of the semiconductor substrate.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: January 7, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Yi Lin, Chih-Chuan Yang, Shih-Hao Lin
  • Patent number: 12178032
    Abstract: A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: December 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Chun Keng, Kuo-Hsiu Hsu, Chih-Chuan Yang, Lien Jung Hung, Ping-Wei Wang
  • Publication number: 20240420945
    Abstract: In some examples, an infrared emitter is provided with a heating layer sandwiched by top and bottom optical layers that allow only narrow-band infrared light to pass through. A reflective layer may be further provided below the bottom optical layers. This configuration greatly reduces the energy loss and can be manufactured with simple method and low cost.
    Type: Application
    Filed: August 27, 2024
    Publication date: December 19, 2024
    Inventors: Ching-Fuh Lin, Chung-Hua Chao, Po-Chuan Yang
  • Patent number: 12160985
    Abstract: Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: December 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ping-Wei Wang, Chih-Chuan Yang, Lien Jung Hung, Feng-Ming Chang, Kuo-Hsiu Hsu, Kian-Long Lim, Ruey-Wen Chang
  • Publication number: 20240397694
    Abstract: A semiconductor structure includes a substrate, first channel layers vertically stacked over the substrate in a first region, and second channel layers vertically stacked over the substrate in a second region. The first and second regions have opposite conductivity types. The semiconductor structure also includes a threshold voltage (Vt) modulation layer wrapping around each of the second channel layers in the second region. The first region is free of the Vt modulation layer. The semiconductor structure also includes a gate dielectric layer wrapping around each of the first channel layers and the second channel layers over the Vt modulation layer, and a work function metal layer disposed on the gate dielectric layer and wrapping around each of the first channel layers and the second channel layers.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Inventors: Shih-Hao Lin, Chih-Hsiang Huang, Shang-Rong Li, Chih-Chuan Yang, Jui-Lin Chen, Ming-Shuan Li
  • Publication number: 20240388951
    Abstract: Methods and apparatus are disclosed for wireless transmission of a data packet. An optimization problem is formulated—based on channel condition, latency requirement, and/or packet size—and solved to jointly determine values of multiple transmission parameters such as slot size, subcarrier spacing, modulation scheme, or coding rate. Dynamic programming can solve the problem efficiently. Retransmission is supported. Reliability can be maximized subject to a latency constraint, to provide ultra-reliable low-latency communication. Variations, results, and applications are presented.
    Type: Application
    Filed: May 16, 2023
    Publication date: November 21, 2024
    Applicant: UVic Industry Partnerships Inc.
    Inventors: Negin Sadat Saatchi, Hong-Chuan Yang
  • Publication number: 20240387671
    Abstract: A semiconductor device structure includes nanostructures disposed over a substrate. The structure also includes a gate structure surrounding the nanostructures. The structure also includes inner spacers disposed over opposite sides of the gate structure. The structure also includes source/drain epitaxial structure disposed over opposite sides of the nanostructures. An air gap is disposed between the inner spacers and the source/drain epitaxial structure.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Shih-Hao Lin, Chih-Chuan Yang
  • Publication number: 20240387546
    Abstract: A semiconductor structure includes a first transistor and a second transistor. The first transistor includes a first fin structure and a first metal gate over the first fin structure. The first metal gate includes a first work function metal layer and a first gap-filling metal layer. The second transistor includes a second fin structure and a second metal gate over the second fin structure. The second metal gate includes a second work function metal layer and a second gap-filling metal layer. The first metal gate and the second metal gate provide a same work function. A width of the first metal gate is equal to a width of the second metal gate. A width of a top surface of the first gap-filling metal layer is greater than a width of a top surface of the second gap-filling metal layer.
    Type: Application
    Filed: May 18, 2023
    Publication date: November 21, 2024
    Inventors: PO-YING CHANG, WEN-LANG WU, CHANG-TAI LEE, LI-CHUNG KUO, YUN-HAN LIN, CHEN-CHUAN YANG
  • Publication number: 20240379444
    Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.
    Type: Application
    Filed: July 14, 2024
    Publication date: November 14, 2024
    Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Kian-Long Lim, Chih-Wei Lee, Chien-Yuan Chen, Jo-Chun Hung, Yung-Hsiang Chan, Yu-Kuan Lin, Lien-Jung Hung
  • Publication number: 20240379801
    Abstract: A method includes providing a substrate having a first region and a second region, forming a fin protruding from the first region, where the fin includes a first SiGe layer and a stack alternating Si layers and second SiGe layers disposed over the first SiGe layer and the first SiGe layer has a first concentration of Ge and each of the second SiGe layers has a second concentration of Ge that is greater than the first concentration, recessing the fin to form an S/D recess, recessing the first SiGe layer and the second SiGe layers exposed in the S/D recess, where the second SiGe layers are recessed more than the first SiGe layer, forming an S/D feature in the S/D recess, removing the recessed first SiGe layer and the second SiGe layers to form openings, and forming a metal gate structure over the fin and in the openings.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Kian-Long Lim, Chih-Hsuan Chen, Ping-Wei Wang
  • Publication number: 20240379851
    Abstract: A semiconductor device includes a memory macro having a middle strap area between edges of the memory macro and memory bit areas on both sides of the middle strap area. The memory macro includes n-type wells and p-type wells arranged alternately along a first direction with well boundaries between the adjacent n-type and p-type wells. The n-type and the p-type wells extend lengthwise along a second direction and extend continuously through the middle strap area and the memory bit areas. The memory macro includes a first dielectric layer disposed at the well boundaries in the middle strap area and the memory bit areas. From a top view, the first dielectric layer extends along the second direction and fully separates the n-type wells from the p-type wells in the middle strap area. From a cross-sectional view, the first dielectric layer vertically extends into the n-type or the p-type wells.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Hsin-Wen Su, Yu-Kuan Lin, Chih-Chuan Yang, Chang-Ta Yang, Shih-Hao Lin
  • Patent number: 12142684
    Abstract: A semiconductor device includes a memory macro having a middle strap area between edges of the memory macro and memory bit areas on both sides of the middle strap area. The memory macro includes n-type wells and p-type wells arranged alternately along a first direction with well boundaries between the adjacent n-type and p-type wells. The n-type and the p-type wells extend lengthwise along a second direction and extend continuously through the middle strap area and the memory bit areas. The memory macro includes a first dielectric layer disposed at the well boundaries in the middle strap area and the memory bit areas. From a top view, the first dielectric layer extends along the second direction and fully separates the n-type wells from the p-type wells in the middle strap area. From a cross-sectional view, the first dielectric layer vertically extends into the n-type or the p-type wells.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Wen Su, Yu-Kuan Lin, Chih-Chuan Yang, Chang-Ta Yang, Shih-Hao Lin
  • Publication number: 20240371696
    Abstract: A semiconductor structure includes a substrate, a fin-shaped structure protruding from the substrate and orienting lengthwise along a first direction, an isolation feature disposed over the substrate and along a sidewall of a bottom portion of the fin-shaped structure, and a metal gate structure disposed over the fin-shaped structure and the isolation feature and orienting lengthwise along a second direction perpendicular to the first direction. The metal gate structure includes a bottom portion sandwiched between the isolation feature and the bottom portion of the fin-shaped structure along the second direction.
    Type: Application
    Filed: July 12, 2024
    Publication date: November 7, 2024
    Inventors: Chih-Chuan Yang, Chia-Hao Pao, Shih-Hao Lin, Shang-Rong Li, Kuo-Hsiu Hsu, Ping-Wei Wang
  • Publication number: 20240371972
    Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a protruding portion of a substrate, isolation features disposed over the substrate, wherein a top surface of the protruding portion of the substrate is separated from a bottom surface of the isolation features by a first distance, a metal gate stack interleaved with the stack of semiconductor layers, where a bottom portion of the metal gate stack is disposed on sidewalls of the protruding portion of the substrate and where thickness of the bottom portion of the metal gate stack is defined by a second distance that is less than the first distance, and epitaxial source/drain features disposed adjacent to the metal gate stack.
    Type: Application
    Filed: July 12, 2024
    Publication date: November 7, 2024
    Inventors: Shih-Hao Lin, Chih-Chuan Yang, Hsin-Wen Su, Jing-Yi Lin, Shang-Rong Li, Chong-De Lien
  • Publication number: 20240371437
    Abstract: A memory device is provided. The memory device includes a memory cell array having a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of columns include a first plurality of memory cells connected to a first bit line and a second bit line. A pre-charge circuit is connected to the memory cell array. The pre-charge circuit pre-charges each of the first bit line and the second bit line from a first end. A pre-charge assist circuit is connected to the memory cell array. The pre-charge assist circuit pre-charges each of the first bit line and the second bit line from a second end, the second end being opposite the first end.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao PAO, Kian-Long LIM, Chih-Chuan YANG, Jui-Wen CHANG, Chao-Yuan CHANG, Feng-Ming CHANG, Lien-Jung HUNG, Ping-Wei WANG
  • Publication number: 20240373614
    Abstract: An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.
    Type: Application
    Filed: July 12, 2024
    Publication date: November 7, 2024
    Inventors: Shih-Hao Lin, Chih-Chuan Yang, Hsin-Wen Su, Kian-Long Lim, Chien-Chih Lin
  • Patent number: 12122021
    Abstract: An angle adjustment structure for pressing a hand tool comprising: a first handle, a second handle, a first spring washer, a second spring washer, a return spring, a first presser, a second presser, a first fastener and a second fastener. The first handle includes a contact sheet having a first thickness, a first toothed orifice. The second handle includes a groove having a second thickness, a second toothed orifice, a first fixing plate and a second fixing plate. A profile of the second toothed orifice is identical to a profile of the first toothed orifice. The return spring is defined on the first presser and the second presser. The first handle and the second handle adjust the angle when the first presser and second presser are pressed simultaneously, and being fixed by the first fastener and second fastener to avoid a removal.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: October 22, 2024
    Inventor: Te-Chuan Yang
  • Publication number: 20240347642
    Abstract: A method of fabricating a device includes providing a fin extending from a substrate in a device type region, where the fin includes a plurality of semiconductor channel layers. In some embodiments, the method further includes forming a gate structure over the fin. Thereafter, in some examples, the method includes removing a portion of the plurality of semiconductor channel layers within a source/drain region adjacent to the gate structure to form a trench in the source/drain region. In some cases, the method further includes after forming the trench, depositing an adhesion layer within the source/drain region along a sidewall surface of the trench. In various embodiments, and after depositing the adhesion layer, the method further includes epitaxially growing a continuous first source/drain layer over the adhesion layer along the sidewall surface of the trench.
    Type: Application
    Filed: June 26, 2024
    Publication date: October 17, 2024
    Inventors: Shih-Hao Lin, Chong-De Lien, Chih-Chuan Yang, Chih-Yu Hsu, Ming-Shuan Li, Hsin-Wen Su
  • Publication number: 20240339449
    Abstract: A device includes a first and a second stacks of channel layers each extending from a first height to a second height. A first dielectric feature on a first side of the first stack and between the first and the second stacks extends from a third height to a fourth height. A second dielectric feature on a second side of the first stack opposite to the first side extends from the third height to a fifth height. A gate electrode extends continuously across a top surface of the first and the second stacks and extends to a sixth height. The fifth height is above the sixth height, the sixth height is above the second height, the second height is above the fourth height, the fourth height is above the first height, and the first height is above the third height.
    Type: Application
    Filed: June 20, 2024
    Publication date: October 10, 2024
    Inventors: Chia-Hao Pao, Chih-Chuan Yang, Chih-Hsuan Chen, Shih-Hao Lin
  • Patent number: D1056655
    Type: Grant
    Filed: February 2, 2023
    Date of Patent: January 7, 2025
    Inventor: Te-Chuan Yang