Patents by Inventor Chuan Yang

Chuan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230408077
    Abstract: Disclosed are a flexible wire support structure and a lamp conductor-cable using the same, which is formed of a first flexible wire and a second flexible wire that are arranged adjacent to and in juxtaposition with each other. An enclosure binding layer encloses an outside of the first and second flexible wires. At least one supporting body is arranged between the adjacent first and second flexible wires. The supporting body has two surfaces that are respectively formed with a first receiving groove and a second receiving groove extending along an axis line of the first and second flexible wires. The first and second receiving grooves receive the adjacent first and second flexible wires to dispose therein so as to have the supporting body filled between the adjacent first and second flexible wires, to realize supporting and constraining of the adjacent flexible wires.
    Type: Application
    Filed: June 20, 2022
    Publication date: December 21, 2023
    Inventor: Chuan-Yang Lee
  • Publication number: 20230387326
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 30, 2023
    Inventors: Chih-Chuan Yang, Kuo-Hsiu Hsu
  • Publication number: 20230378365
    Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 23, 2023
    Inventors: Shih-Hao LIN, Chih-Chuan YANG, Chih-Hsuan CHEN, Bwo-Ning CHEN, Cha-Hon CHOU, Hsin-Wen SU, Chih-Hsiang HUANG
  • Publication number: 20230369496
    Abstract: A semiconductor device includes a memory macro having a middle strap area between edges of the memory macro and memory bit areas on both sides of the middle strap area. The memory macro includes n-type wells and p-type wells arranged alternately along a first direction with well boundaries between the adjacent n-type and p-type wells. The n-type and the p-type wells extend lengthwise along a second direction and extend continuously through the middle strap area and the memory bit areas. The memory macro includes a first dielectric layer disposed at the well boundaries in the middle strap area and the memory bit areas. From a top view, the first dielectric layer extends along the second direction and fully separates the n-type wells from the p-type wells in the middle strap area. From a cross-sectional view, the first dielectric layer vertically extends into the n-type or the p-type wells.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Inventors: Hsin-Wen Su, Yu-Kuan Lin, Chih-Chuan Yang, Chang-Ta Yang, Shih-Hao Lin
  • Publication number: 20230369143
    Abstract: A test structure on a wafer is provided. The test structure includes a plurality of cells under test, a first output pad and a second output pad coupled to different cells, a plurality of first input pads, and a plurality of second input pads. The cells are arranged in rows and columns of a test array. Each of the first input pads is coupled to the cells in respective column of the test array. Each of the second input pads is coupled to the cells in respective row of the test array. A first voltage is applied to one of the first input pads and a second voltage is applied to one of the second input pads to turn on a cell, and a current flowing through the turned-on cell is measured.
    Type: Application
    Filed: June 28, 2023
    Publication date: November 16, 2023
    Inventors: Jing-Yi LIN, Chih-Chuan YANG, Kuo-Hsiu HSU, Lien-Jung HUNG
  • Publication number: 20230371225
    Abstract: A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells is connected to a word line to apply a first signal to select the memory cell to read data from or write the data to the memory cell and a bit line to read the data from the memory cell or provide the data to write to the memory cell upon selecting the memory cell by the word line. A first bit line portion of the bit line connected to a first memory cell of the plurality of memory cells abuts a second bit line portion of the bit line connected to a second memory cell of the plurality of memory cells. The first memory cell is adjacent to the second memory cell.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ping-Wei Wang, Lien-Jung Hung, Kuo-Hsiu Hsu, Kian-Long Lim, Yu-Kuan LIN, Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Choh Fei Yeap
  • Publication number: 20230363133
    Abstract: A semiconductor device includes a first memory cell and a dummy region adjacent to the first memory cell. The first memory cell includes a first transistor. The dummy region includes a cut-off transistor. The cut-off transistor has a first terminal electrically coupled to a second terminal of the first transistor. The cut-off transistor has a third terminal electrically coupled to ground.
    Type: Application
    Filed: July 6, 2023
    Publication date: November 9, 2023
    Inventor: Chih-Chuan Yang
  • Publication number: 20230354573
    Abstract: The present disclosure describes a memory structure including a memory cell array. The memory cell array includes memory cells and first n-type wells extending in a first direction. The memory structure also includes a second n-type well formed in a peripheral region of the memory structure. The second n-type well extends in a second direction and is in contact with a first n-type well of the first n-type wells. The memory structure further includes a pick-up region formed in the second n-type well. The pick-up region is electrically coupled to the first n-type well of first n-type wells.
    Type: Application
    Filed: April 28, 2022
    Publication date: November 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chuan Yang, Chao-Yuan CHANG, Shih-Hao LIN, Chia-Hao PAO, Feng-Ming CHANG, Lien-Jung HUNG, Ping-Wei WANG
  • Publication number: 20230337624
    Abstract: A pet carrier stroller is revealed. The pet carrier stroller mainly includes a seat cushion with two support rods, a pet carrier bag connected with the seat cushion, and a stroller. While in use, the seat cushion together with the pet carrier bag having a pet therein is disposed on a mounting frame of the stroller. Then the pet carrier bag is arranged at the stroller firmly by anchor members of the two support rods of the seat cushion connected and fastened with fastening portions of the mounting frame of the stroller correspondingly so that safety of pets travelled in the stroller is improved. Moreover, the seat cushion and the stroller are disconnected. Then a front-wheel support and a rear-wheel support of the stroller are pulled together toward each other for reducing space occupied and convenient storage.
    Type: Application
    Filed: April 22, 2022
    Publication date: October 26, 2023
    Inventor: YUNG-CHUAN YANG
  • Publication number: 20230331988
    Abstract: Techniques regarding guanidinium functionalized polylysine polymers that can have antimicrobial and/or anticancer activity are provided. For example, one or more embodiments described herein can comprise a chemical composition, which can comprise a polymer comprising a molecular backbone covalently bonded to a pendent guanidinium functional group, wherein the molecular backbone can comprise a polylysine structure.
    Type: Application
    Filed: June 12, 2023
    Publication date: October 19, 2023
    Inventors: Nathaniel H. Park, James L. Hedrick, Victoria A. Piunova, Gavin Jones, Yi Yan Yang, Pang Kern Jeremy Tan, Chuan Yang, Cherylette Anne Alexander
  • Patent number: 11791214
    Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Kian-Long Lim, Chih-Wei Lee, Chien-Yuan Chen, Jo-Chun Hung, Yung-Hsiang Chan, Yu-Kuan Lin, Lien Jung Hung
  • Patent number: 11791422
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chuan Yang, Kuo-Hsiu Hsu
  • Patent number: 11777016
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a source feature and a drain feature, a channel structure disposed between the source feature and the drain feature, a semiconductor layer disposed over the channel structure and the drain feature, a dielectric layer disposed over the semiconductor layer, a backside source contact over the source feature and extending through the semiconductor layer and the dielectric layer, and a backside power rail disposed over the dielectric layer and in contact with the backside source contact.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Wei Wang, Chih-Chuan Yang, Yu-Kuan Lin, Choh Fei Yeap
  • Patent number: 11766451
    Abstract: Techniques regarding treating one or more microbe infections with combination therapy are provided. For example, one or more embodiments described herein can comprise a method, which can comprise enhancing an antimicrobial activity of an antibiotic by a combination therapy. The combination therapy can comprise the antibiotic and a polycarbonate polymer functionalized with a guanidinium functional group.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: September 26, 2023
    Assignee: International Business Machines Corporation
    Inventors: James L Hedrick, Simone Bianco, Mark Kunitomi, Yi Yan Yang, Xin Ding, Chuan Yang, Zhen Chang Liang, Paola Florez de Sessions, Balamurugan Periaswamy
  • Patent number: 11760638
    Abstract: Provided is a method for preparing a graphene material from an industrial hemp material by laser induction, which uses a skin, a stem and/or a root of industrial hemp as a carbon precursor-containing material and reduce the carbon precursor-containing material into graphene by laser induction, so as to prepare graphene, graphene quantum dots, a graphene mesoporous material and a graphene composite material.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: September 19, 2023
    Assignees: YUNNAN HUAPU QUANTUM MATERIAL CO., LTD, ROI OPTOELECTRONICS TECHNOLOGY CO, LTD., CHONGQING INSTITUTE OF EAST CHINA NORMAL UNIVERSITY, EAST CHINA NORMAL UNIVERSITY
    Inventors: Heping Zeng, Chuan Yang, Mengyun Hu
  • Patent number: 11749340
    Abstract: Semiconductor devices and methods are provided. A semiconductor device of the present disclosure includes a bias source, a memory cell array including a first region adjacent to the bias source and a second region away from the bias source, and a conductive line electrically coupled to the bias source, a first memory cell in the first region and a second memory cell in the second region. The first memory cell is characterized by a first alpha ratio and the second memory cell is characterized by a second alpha ratio smaller than the first alpha ratio.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chuan Yang, Shih-Hao Lin
  • Publication number: 20230267991
    Abstract: One aspect of this description relates to a memory cell. In some embodiments, the memory cell includes a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, and a fifth gate structure that each extend along a first lateral direction, a first active structure extending along a second lateral direction and overlaid by respective first portions of the first to fourth gate structures, a second active structure extending along the second lateral direction and overlaid by respective second portions of the first to fourth gate structures, and a third active structure extending along the second lateral direction and overlaid by respective third portions of the third and fifth gate structures. In some embodiments, the first and second gate structures are aligned with each other, with the fourth and fifth gate structures aligned with a first segment and a second segment of the third gate structure, respectively.
    Type: Application
    Filed: April 25, 2023
    Publication date: August 24, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chuan Yang, Feng-Ming Chang, Kuo-Hsiu Hsu, Ping-Wei Wang
  • Patent number: 11737255
    Abstract: A semiconductor device includes a first memory cell and a dummy region adjacent to the first memory cell. The first memory cell includes a first transistor. The dummy region includes a cut-off transistor. The cut-off transistor has a first terminal electrically coupled to a second terminal of the first transistor. The cut-off transistor has a third terminal electrically coupled to ground.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chih-Chuan Yang
  • Patent number: 11725107
    Abstract: Techniques regarding guanidinium functionalized polylysine polymers that can have antimicrobial and/or anticancer activity are provided. For example, one or more embodiments described herein can comprise a chemical composition, which can comprise a polymer comprising a molecular backbone covalently bonded to a pendent guanidinium functional group, wherein the molecular backbone can comprise a polylysine structure.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: August 15, 2023
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Nathaniel H. Park, James L. Hedrick, Victoria A. Piunova, Gavin Jones, Yi Yan Yang, Pang Kern Jeremy Tan, Chuan Yang, Cherylette Anne Alexander
  • Patent number: 11723363
    Abstract: Techniques regarding polymers with antimicrobial functionality are provided. For example, one or more embodiments described herein can regard a polymer, which can comprise a repeating ionene unit. The repeating ionene unit can comprise a cation distributed along a degradable backbone. The degradable backbone can comprise a terephthalamide structure. Further, the repeating ionene unit can have antimicrobial functionality.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: August 15, 2023
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Mareva B. Fevre, James L. Hedrick, Nathaniel H. Park, Victoria A. Piunova, Pang Kern Jeremy Tan, Chuan Yang, Yi Yan Yang