Patents by Inventor Chuan Yang

Chuan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11948829
    Abstract: A method includes receiving a structure that includes a substrate including a first well region having a first dopant type and a second well region having a second dopant type that is opposite to the first dopant type; and fins extending above the substrate. The method further includes forming a patterned etch mask on the structure, wherein the patterned etch mask provides an opening that is directly above a first fin of the fins, wherein the first fin is directly above the first well region. The method further includes etching the structure through the patterned etch mask, wherein the etching removes the first fin and forms a recess in the substrate that spans from the first well region into the second well region; and forming a dielectric material between remaining portions of the fins and within the recess.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chuan Yang, Chang-Ta Yang
  • Patent number: 11949016
    Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Hao Lin, Chih-Chuan Yang, Chih-Hsuan Chen, Bwo-Ning Chen, Cha-Hon Chou, Hsin-Wen Su, Chih-Hsiang Huang
  • Patent number: 11942145
    Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chuan Yang, Jui-Wen Chang, Feng-Ming Chang, Kian-Long Lim, Kuo-Hsiu Hsu, Lien Jung Hung, Ping-Wei Wang
  • Patent number: 11937415
    Abstract: A method of forming a semiconductor device includes providing a substrate including a circuit region and a well strap region, forming a mandrel extending from the circuit region to the well strap region, depositing mandrel spacers on sidewalls of the mandrel, removing the mandrel in the circuit region, while the mandrel in the well strap region remains intact, patterning the substrate with the mandrel spacers in the circuit region and the mandrel in the well strap region as an etch mask, thereby forming at least a first fin in the circuit region and a second fin in the well strap region, and epitaxially growing a first epitaxial feature over the first fin in the circuit region and a second epitaxial feature over the second fin in the well strap region. A width of the second fin is larger than a width of the first fin.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chuan Yang, Kuo-Hsiu Hsu, Feng-Ming Chang, Wen-Chun Keng, Lien Jung Hung
  • Patent number: 11937416
    Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Shih-Hao Lin, Kian-Long Lim, Chih-Chuan Yang, Chia-Hao Pao, Jing-Yi Lin
  • Patent number: 11925171
    Abstract: A car safety device for pets includes a fixing frame mounted in a seat cushion and a seat cushion cover. The seat cushion with the fixing frame is placed into the seat cushion cover and one end of a support rod of the fixing frame is protruding from the seat cushion cover. While in use, the device is placed on a car seat and an anchor member on the support rod of the fixing frame is connected to a support bar of the car seat. Then a pet carrier bag is disposed on the seat cushion cover and a second connecting member of the pet carrier bag is connected with a first connecting member on the seat cushion cover to fix the pet carrier bag on the present device. Thereby the pet carrier bag is firmly mounted on the car seat and pet safety is improved.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: March 12, 2024
    Inventor: Yung Chuan Yang
  • Patent number: 11908860
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) having a device section and a pick-up section. The IC includes a semiconductor substrate. A first fin of the semiconductor substrate is disposed in the device section. A second fin of the semiconductor substrate is disposed in the pick-up section and laterally spaced from the first fin in a first direction. A gate structure is disposed in the device section and laterally spaced from the second fin in the first direction. The gate structure extends laterally over the semiconductor substrate and the first fin in a second direction perpendicular to the first direction. A pick-up region is disposed on the second fin. The pick-up region continuously extends from a first sidewall of the second fin to a second sidewall of the second fin. The first sidewall is laterally spaced from the second sidewall in the first direction.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang, Wen-Chun Keng, Chih-Chuan Yang, Shih-Hao Lin
  • Patent number: 11908910
    Abstract: Methods and devices that provide a first fin structure, a second fin structure, and a third fin structure disposed over a substrate. A dielectric fin is formed between the first fin structure and the second fin structure, and a conductive line is formed between the second fin structure and the third fin structure.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chuan Yang, Jing-Yi Lin, Hsin-Wen Su, Shih-Hao Lin
  • Patent number: 11910585
    Abstract: Well pick-up (WPU) regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region, a WPU region, a first well extending lengthwise along a first direction through the circuit region and into the WPU region, a second well extending lengthwise along the first direction through the circuit region and into the WPU region, and a third well physically connecting a portion of the first well in the WPU region and a portion of the second well in the WPU region.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chuan Yang, Chang-Ta Yang, Ping-Wei Wang
  • Publication number: 20240021247
    Abstract: In certain aspects, a three-dimensional (3D) memory device includes a stack structure including interleaved conductive layers and dielectric layers and having a core array region and a staircase region in a plan view, one or more channel structures each extending through the core array region of the stack structure, and one or more contact structures each extending through the stack structure, wherein each of the one or more contact structures includes a head portion and a body portion, and a width of the head portion of the respective contact structure is larger than that of the body portion of the respective contact structure.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 18, 2024
    Inventors: Yujun Huang, Chuan Yang, Qian Gao, Xin Zhang
  • Publication number: 20230408077
    Abstract: Disclosed are a flexible wire support structure and a lamp conductor-cable using the same, which is formed of a first flexible wire and a second flexible wire that are arranged adjacent to and in juxtaposition with each other. An enclosure binding layer encloses an outside of the first and second flexible wires. At least one supporting body is arranged between the adjacent first and second flexible wires. The supporting body has two surfaces that are respectively formed with a first receiving groove and a second receiving groove extending along an axis line of the first and second flexible wires. The first and second receiving grooves receive the adjacent first and second flexible wires to dispose therein so as to have the supporting body filled between the adjacent first and second flexible wires, to realize supporting and constraining of the adjacent flexible wires.
    Type: Application
    Filed: June 20, 2022
    Publication date: December 21, 2023
    Inventor: Chuan-Yang Lee
  • Publication number: 20230411216
    Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.
    Type: Application
    Filed: July 31, 2023
    Publication date: December 21, 2023
    Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Kian-Long Lim, Chih-Wei Lee, Chien-Yuan Chen, Jo-Chun Hung, Yung-Hsiang Chan, Yu-Kuan Lin, Lien-Jung Hung
  • Publication number: 20230387326
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 30, 2023
    Inventors: Chih-Chuan Yang, Kuo-Hsiu Hsu
  • Publication number: 20230378365
    Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 23, 2023
    Inventors: Shih-Hao LIN, Chih-Chuan YANG, Chih-Hsuan CHEN, Bwo-Ning CHEN, Cha-Hon CHOU, Hsin-Wen SU, Chih-Hsiang HUANG
  • Publication number: 20230371225
    Abstract: A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells is connected to a word line to apply a first signal to select the memory cell to read data from or write the data to the memory cell and a bit line to read the data from the memory cell or provide the data to write to the memory cell upon selecting the memory cell by the word line. A first bit line portion of the bit line connected to a first memory cell of the plurality of memory cells abuts a second bit line portion of the bit line connected to a second memory cell of the plurality of memory cells. The first memory cell is adjacent to the second memory cell.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ping-Wei Wang, Lien-Jung Hung, Kuo-Hsiu Hsu, Kian-Long Lim, Yu-Kuan LIN, Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Choh Fei Yeap
  • Publication number: 20230369143
    Abstract: A test structure on a wafer is provided. The test structure includes a plurality of cells under test, a first output pad and a second output pad coupled to different cells, a plurality of first input pads, and a plurality of second input pads. The cells are arranged in rows and columns of a test array. Each of the first input pads is coupled to the cells in respective column of the test array. Each of the second input pads is coupled to the cells in respective row of the test array. A first voltage is applied to one of the first input pads and a second voltage is applied to one of the second input pads to turn on a cell, and a current flowing through the turned-on cell is measured.
    Type: Application
    Filed: June 28, 2023
    Publication date: November 16, 2023
    Inventors: Jing-Yi LIN, Chih-Chuan YANG, Kuo-Hsiu HSU, Lien-Jung HUNG
  • Publication number: 20230369496
    Abstract: A semiconductor device includes a memory macro having a middle strap area between edges of the memory macro and memory bit areas on both sides of the middle strap area. The memory macro includes n-type wells and p-type wells arranged alternately along a first direction with well boundaries between the adjacent n-type and p-type wells. The n-type and the p-type wells extend lengthwise along a second direction and extend continuously through the middle strap area and the memory bit areas. The memory macro includes a first dielectric layer disposed at the well boundaries in the middle strap area and the memory bit areas. From a top view, the first dielectric layer extends along the second direction and fully separates the n-type wells from the p-type wells in the middle strap area. From a cross-sectional view, the first dielectric layer vertically extends into the n-type or the p-type wells.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Inventors: Hsin-Wen Su, Yu-Kuan Lin, Chih-Chuan Yang, Chang-Ta Yang, Shih-Hao Lin
  • Publication number: 20230363133
    Abstract: A semiconductor device includes a first memory cell and a dummy region adjacent to the first memory cell. The first memory cell includes a first transistor. The dummy region includes a cut-off transistor. The cut-off transistor has a first terminal electrically coupled to a second terminal of the first transistor. The cut-off transistor has a third terminal electrically coupled to ground.
    Type: Application
    Filed: July 6, 2023
    Publication date: November 9, 2023
    Inventor: Chih-Chuan Yang
  • Publication number: 20230354573
    Abstract: The present disclosure describes a memory structure including a memory cell array. The memory cell array includes memory cells and first n-type wells extending in a first direction. The memory structure also includes a second n-type well formed in a peripheral region of the memory structure. The second n-type well extends in a second direction and is in contact with a first n-type well of the first n-type wells. The memory structure further includes a pick-up region formed in the second n-type well. The pick-up region is electrically coupled to the first n-type well of first n-type wells.
    Type: Application
    Filed: April 28, 2022
    Publication date: November 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chuan Yang, Chao-Yuan CHANG, Shih-Hao LIN, Chia-Hao PAO, Feng-Ming CHANG, Lien-Jung HUNG, Ping-Wei WANG
  • Publication number: 20230337624
    Abstract: A pet carrier stroller is revealed. The pet carrier stroller mainly includes a seat cushion with two support rods, a pet carrier bag connected with the seat cushion, and a stroller. While in use, the seat cushion together with the pet carrier bag having a pet therein is disposed on a mounting frame of the stroller. Then the pet carrier bag is arranged at the stroller firmly by anchor members of the two support rods of the seat cushion connected and fastened with fastening portions of the mounting frame of the stroller correspondingly so that safety of pets travelled in the stroller is improved. Moreover, the seat cushion and the stroller are disconnected. Then a front-wheel support and a rear-wheel support of the stroller are pulled together toward each other for reducing space occupied and convenient storage.
    Type: Application
    Filed: April 22, 2022
    Publication date: October 26, 2023
    Inventor: YUNG-CHUAN YANG