Patents by Inventor Chul Hong Park

Chul Hong Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200057830
    Abstract: An integrated circuit including a standard cell includes: a plurality of first wells extending in a first horizontal direction with a first width and of a first conductivity type; and a plurality of second wells extending in the first horizontal direction with a second width and having a second conductivity type, wherein the plurality of first wells and the plurality of second wells are alternately arranged in a second horizontal direction that is orthogonal to the first horizontal direction, and when m and n are integers greater than or equal to 3, the standard cell has a length in the second horizontal direction, the length being equal to a sum of m times a half of the first width and n times a half of the second width.
    Type: Application
    Filed: May 2, 2019
    Publication date: February 20, 2020
    Inventors: Raheel Azmat, Sidharth Rastogi, Chul-hong Park, Jae-seok Yang, Kwan-young Chun
  • Patent number: 10546855
    Abstract: Integrated circuit devices are provided. The IC devices may include an active region extending in a first direction, first and second gate electrodes extending in a second direction, a first impurity region in the active region adjacent a first side of the first gate electrode, a second impurity region in the active region between a second side of the first gate electrode and a first side of the second gate electrode, a third impurity region in the active region adjacent a second side of the second gate electrode, a cross gate contact electrically connecting the first and second impurity regions, a first contact electrically connected to the third impurity region, a first wire electrically connected to the cross gate contact, and a second wire electrically connected to the first contact. The first and second wires may extend only in the first direction and may be on the same line.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: January 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Rajeev Ranjan, Deepak Sharma, Subhash Kuchanuri, Chul Hong Park, Jae Seok Yang, Kwan Young Chun
  • Publication number: 20190383952
    Abstract: The present invention relates to a water dosimetry device using X-ray induced ultrasonic waves, in which a medical X-ray linear accelerator and an ultrasonic transducer are combined to construct a medical X-ray linear accelerator-based ultrasound imaging device, so that a radiation-absorbed dose in water when X-rays irradiate the water is measured in real time.
    Type: Application
    Filed: February 2, 2018
    Publication date: December 19, 2019
    Inventors: Chul Hong KIM, In Jung KIM, Byoung Chul KIM, Eun Yeong PARK, Chul Yong YI, Jeesu KIM, Yuhan JUNG, Joong Hyun KIM
  • Patent number: 10497645
    Abstract: A semiconductor device includes a first conductive element, a first insulating layer and a second insulating layer sequentially disposed on the first conductive element, a conductive via passing through the first insulating layer and the second insulating layer. The conductive via is connected to the first conductive element. The semiconductor device includes a via extension portion disposed in the second insulating layer that extends along an upper surface of the first insulating layer from one side surface of the conductive via, and a second conductive element disposed on the second insulating layer that is connected to the via extension portion.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: December 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yubo Qian, Byung Sung Kim, Hyeon Uk Kim, Young Gook Park, Chul Hong Park
  • Publication number: 20190354655
    Abstract: A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.
    Type: Application
    Filed: August 1, 2019
    Publication date: November 21, 2019
    Inventors: Chul-Hong Park, Su-Hyeon Kim, Sharma Deepak
  • Patent number: 10474783
    Abstract: A method of designing a layout of a semiconductor device includes designing layouts of cells, each layout including first conductive lines, the first conductive lines extending in a first direction and being spaced apart from each other in a second direction crossing the first direction, disposing the layouts of the cells to be adjacent to each other in the first direction, such that the first conductive lines in adjacent layouts of the cells are connected to each other, and disposing insulation blocks at a boundary area between adjacent ones of the layouts of the cells or in areas of the layouts of the cells adjacent to the boundary area, such that the insulation blocks block connections between some of the first conductive lines.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: November 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sidharth Rastogi, Subhash Kuchanuri, Chul-Hong Park, Jae-Seok Yang
  • Publication number: 20190326285
    Abstract: An integrated circuit device includes a substrate including a fin active region extending in a first direction, a gate line intersecting the fin active region and extending in a second direction perpendicular to the first direction, a power line electrically connected to source/drain regions at sides of the gate line on the fin active region, a pair of dummy gate lines intersecting the fin active region and extending in the second direction, and a device separation structure electrically connected to the pair of dummy gate lines and including a lower dummy contact plug between the pair of dummy gate lines on the fin active region and electrically connected to the power line, and an upper dummy contact plug on the lower dummy contact plug and on the pair of dummy gate lines to electrically connect the lower dummy contact plug to the pair of dummy gate lines.
    Type: Application
    Filed: June 26, 2019
    Publication date: October 24, 2019
    Inventors: Sidharth RASTOGI, Subhash KUCHANURI, Raheel AZMAT, Pan-jae PARK, Chul-hong PARK, Jae-seok YANG, Kwan-young CHUN
  • Patent number: 10403619
    Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes first and second logic cells adjacent to each other in a first direction on a substrate, a gate electrode extending in the first direction in each of the first and second logic cells, a power line extending in a second direction at a boundary between the first and second logic cells, and a connection structure electrically connecting the power line to an active pattern of the first logic cell and to an active pattern of the second logic cell. The connection structure lies below the power line and extends from the first logic cell to the second logic cell. A top surface of the connection structure is at a higher level than that of a top surface of the gate electrode.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yubo Qian, Byung-Sung Kim, Chul-Hong Park, Haewang Lee
  • Patent number: 10402528
    Abstract: A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chul-Hong Park, Su-Hyeon Kim, Sharma Deepak
  • Publication number: 20190252380
    Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Deepak SHARMA, Hyun-jong Lee, Raheel Azmat, Chul-hong Park, Sang-jun Park
  • Patent number: 10361198
    Abstract: An integrated circuit device includes a substrate including a fin active region extending in a first direction, a gate line intersecting the fin active region and extending in a second direction perpendicular to the first direction, a power line electrically connected to source/drain regions at sides of the gate line on the fin active region, a pair of dummy gate lines intersecting the fin active region and extending in the second direction, and a device separation structure electrically connected to the pair of dummy gate lines and including a lower dummy contact plug between the pair of dummy gate lines on the fin active region and electrically connected to the power line, and an upper dummy contact plug on the lower dummy contact plug and on the pair of dummy gate lines to electrically connect the lower dummy contact plug to the pair of dummy gate lines.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: July 23, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sidharth Rastogi, Subhash Kuchanuri, Raheel Azmat, Pan-jae Park, Chul-hong Park, Jae-seok Yang, Kwan-young Chun
  • Publication number: 20190221563
    Abstract: An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending in a second direction that intersects the first direction on the fin-type active region; a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween and extending in the second direction to be aligned with the insulating separation structure; a pair of source/drain regions located on the fin-type active region and spaced apart from each other with the insulating separation structure therebetween; and a jumper contact located over the insulating separation structure and connected between the pair of source/drain regions.
    Type: Application
    Filed: March 25, 2019
    Publication date: July 18, 2019
    Inventors: Jung-hyuck CHOI, Hae-wang LEE, Hyoun-jee HA, Chul-hong PARK
  • Patent number: 10319720
    Abstract: An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending in a second direction that intersects the first direction on the fin-type active region; a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween and extending in the second direction to be aligned with the insulating separation structure; a pair of source/drain regions located on the fin-type active region and spaced apart from each other with the insulating separation structure therebetween; and a jumper contact located over the insulating separation structure and connected between the pair of source/drain regions.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-hyuck Choi, Hae-wang Lee, Hyoun-jee Ha, Chul-hong Park
  • Patent number: 10297596
    Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Deepak Sharma, Hyun-jong Lee, Raheel Azmat, Chul-hong Park, Sang-jun Park
  • Publication number: 20190148292
    Abstract: A semiconductor device includes a first conductive element, a first insulating layer and a second insulating layer sequentially disposed on the first conductive element, a conductive via passing through the first insulating layer and the second insulating layer. The conductive via is connected to the first conductive element. The semiconductor device includes a via extension portion disposed in the second insulating layer that extends along an upper surface of the first insulating layer from one side surface of the conductive via, and a second conductive element disposed on the second insulating layer that is connected to the via extension portion.
    Type: Application
    Filed: January 10, 2019
    Publication date: May 16, 2019
    Inventors: Yubo Qian, Byung Sung Kim, Hyeon Uk Kim, Young Gook Park, Chul Hong Park
  • Publication number: 20190146138
    Abstract: Disclosed is a lighting device which comprises: an optical member comprising a protruding optical pattern forming a gap with an adjacent layer; at least one light emitting unit inserted into the optical member; and a resin layer formed on the optical member and the at least one light emitting unit, whereby it is possible to obtain an effect that the shapes of light change depending on the viewing angle when viewing the light source by producing various protruding optical patterns, an effect that the whole thickness can be reduced, and an effect that the degree of design freedom can be enhanced when designing products thanks to an enhanced flexibility.
    Type: Application
    Filed: January 17, 2019
    Publication date: May 16, 2019
    Inventors: HYUN DUCK YANG, JIN HEE KIM, CHUL HONG KIM, GWANG HO PARK, MOO RYOUNG PARK
  • Publication number: 20190122988
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.
    Type: Application
    Filed: December 12, 2018
    Publication date: April 25, 2019
    Inventors: Hyo-Jin KIM, Chang-Hwa KIM, Hwi-Chan JUN, Chul-Hong PARK, Jae-Seok YANG, Kwan-Young CHUN
  • Publication number: 20190109088
    Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.
    Type: Application
    Filed: November 27, 2018
    Publication date: April 11, 2019
    Inventors: Vincent Chun Fai LAU, Jung-ho DO, Byung-sung KIM, Chul-hong PARK
  • Patent number: 10249605
    Abstract: An integrated circuit (IC) device includes at least one standard cell. The at least one standard cell includes: first and second active regions respectively disposed on each of two sides of a dummy region, the first and second active regions having different conductivity types and extending in a first direction; first and second gate lines extending parallel to each other in a second direction perpendicular to the first direction across the first and second active regions, a first detour interconnection structure configured to electrically connect the first gate line with the second gate line; and a second detour interconnection structure configured to electrically connect the second gate line with the first gate line. The first and second detour interconnection structures include a lower interconnection layer extending in the first direction, an upper interconnection layer extending in the second direction, and a contact via.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: April 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kuchanuri Subhash, Rastogi Sidharth, Deepak Sharma, Chul-hong Park, Jae-seok Yang
  • Patent number: 10217705
    Abstract: A semiconductor device includes a first conductive element, a first insulating layer and a second insulating layer sequentially disposed on the first conductive element, a conductive via passing through the first insulating layer and the second insulating layer. The conductive via is connected to the first conductive element. The semiconductor device includes a via extension portion disposed in the second insulating layer that extends along an upper surface of the first insulating layer from one side surface of the conductive via, and a second conductive element disposed on the second insulating layer that is connected to the via extension portion.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: February 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yubo Qian, Byung Sung Kim, Hyeon Uk Kim, Young Gook Park, Chul Hong Park