Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.

Abstract: An integrated circuit including a standard cell includes: a plurality of first wells extending in a first horizontal direction with a first width and of a first conductivity type; and a plurality of second wells extending in the first horizontal direction with a second width and having a second conductivity type, wherein the plurality of first wells and the plurality of second wells are alternately arranged in a second horizontal direction that is orthogonal to the first horizontal direction, and when m and n are integers greater than or equal to 3, the standard cell has a length in the second horizontal direction, the length being equal to a sum of m times a half of the first width and n times a half of the second width.

Abstract: A semiconductor device includes a substrate including a first side and a second side opposite to the first side, a first power rail and a second power rail provided on the first side of the substrate, the first power rail and the second power rail extending in a first direction and being separated in a second direction, a first active region and a second active region provided on the first side of the substrate, the first active region and the second active region being defined by an element separation film between the first power rail and the second power rail and being separated in the second direction, a power delivery network provided on the second side of the substrate, and a first power through via penetrating the element separation film and the substrate, the first power through via connecting the power delivery network and the first power rail.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first side and a second side that are opposite to each other, a power tap cell in a first row, a second row adjacent to the first row, and a third row adjacent to the second row, on the first side of the substrate, a first power rail and a second power rail on the power tap cell, that extend in a first direction and are spaced apart from each other in a second direction, and a power delivery network on the second side of the substrate. The power tap cell includes a first power through via that penetrates the substrate and extends from the power delivery network to the first power rail, and a second power through via that penetrates the substrate and extends from the power delivery network to the second power rail.

Abstract: This application is directed to cooling a semiconductor system. The semiconductor system includes a device substrate having a first surface and a second surface, an electronic component thermally coupled to the device substrate, and a cooling substrate coupled to the device substrate. The cooling substrate includes a third surface facing the second surface of the device substrate, a fourth surface opposite the third surface, and a plurality of vias between the third and fourth surfaces. The second surface and the third surface define a cavity therebetween, such that in use coolant flows from the fourth surface through the plurality of vias to exit at the third surface, enters the cavity between the second and third surfaces, and impinges on the second surface. At least a portion of one or more of the device substrate and the cooling substrate have similar coefficients of thermal expansion.

Abstract: An integrated circuit including a standard cell includes: a plurality of first wells extending in a first horizontal direction with a first width and of a first conductivity type; and a plurality of second wells extending in the first horizontal direction with a second width and having a second conductivity type, wherein the plurality of first wells and the plurality of second wells are alternately arranged in a second horizontal direction that is orthogonal to the first horizontal direction, and when m and n are integers greater than or equal to 3, the standard cell has a length in the second horizontal direction, the length being equal to a sum of m times a half of the first width and n times a half of the second width.

Abstract: An integrated circuit including a standard cell includes: a plurality of first wells extending in a first horizontal direction with a first width and of a first conductivity type; and a plurality of second wells extending in the first horizontal direction with a second width and having a second conductivity type, wherein the plurality of first wells and the plurality of second wells are alternately arranged in a second horizontal direction that is orthogonal to the first horizontal direction, and when m and n are integers greater than or equal to 3, the standard cell has a length in the second horizontal direction, the length being equal to a sum of m times a half of the first width and n times a half of the second width.

Abstract: An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending in a second direction that intersects the first direction on the fin-type active region; a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween and extending in the second direction to be aligned with the insulating separation structure; a pair of source/drain regions located on the fin-type active region and spaced apart from each other with the insulating separation structure therebetween; and a jumper contact located over the insulating separation structure and connected between the pair of source/drain regions.

Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

Abstract: This application is directed to methods and devices for an efficient power amplification system. An electronic device includes a first and a second power amplifier that are coupled to a quadrature combiner, a temperature monitoring circuit coupled to the first and second power amplifiers, and a controller coupled to the temperature monitoring circuit. The temperature monitoring circuit is configured to determine a temperature difference between the first and second power amplifiers. The controller is configured to adjust operation of at least one of the first and second power amplifiers to reduce the temperature difference between the first and second power amplifiers.

Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

Abstract: The semiconductor chip includes a semiconductor substrate having a surface, a circuit formed on the surface, and a plurality of pillars coupled to the surface adjacent to the circuit. The plurality of pillars is thermally conductive and is thermally coupled to the circuit so as to dissipate heat generated by the circuit. The semiconductor substrate, circuit, and plurality of pillars are integral parts of the integrated semiconductor chip. A method of fabricating the integrated semiconductor chip includes providing a semiconductor substrate having a surface. The method includes forming a circuit on the surface, and forming a plurality of pillars thermally coupled to the surface adjacent to the circuit.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.

Abstract: A semiconductor device includes a plurality of main contact plugs and a plurality of dummy contact plugs which pass through an insulating layer on a substrate. A plurality of upper interconnections is on the insulating layer. The plurality of dummy contact plugs include a first dummy contact plug. The plurality of upper interconnections include a first upper interconnection overlapping the first dummy contact plug. A vertical central axis of the first dummy contact plug is located outside the first upper interconnection.

Abstract: An integrated circuit device includes a substrate including a fin active region extending in a first direction, a gate line intersecting the fin active region and extending in a second direction perpendicular to the first direction, a power line electrically connected to source/drain regions at sides of the gate line on the fin active region, a pair of dummy gate lines intersecting the fin active region and extending in the second direction, and a device separation structure electrically connected to the pair of dummy gate lines and including a lower dummy contact plug between the pair of dummy gate lines on the fin active region and electrically connected to the power line, and an upper dummy contact plug on the lower dummy contact plug and on the pair of dummy gate lines to electrically connect the lower dummy contact plug to the pair of dummy gate lines.

Abstract: A semiconductor device includes first to fourth cells sequentially disposed on a substrate, first to third diffusion break structures, a first fin structure configured to protrude from the substrate, the first fin structure comprising first to fourth fins separated from each other by the first to third diffusion break structures, a second fin structure configured to protrude from the substrate, to be spaced apart from the first fin structure, the second fin structure comprising fifth to eighth fins separated from each other by the first to third diffusion break structures, the first to fourth gate electrodes being disposed in the first to fourth cells, respectively, and the number of fins in one cell of the first to fourth cells is different from the number of fins in an other cell of the first to fourth cells.

Abstract: An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending in a second direction that intersects the first direction on the fin-type active region; a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween and extending in the second direction to be aligned with the insulating separation structure; a pair of source/drain regions located on the fin-type active region and spaced apart from each other with the insulating separation structure therebetween; and a jumper contact located over the insulating separation structure and connected between the pair of source/drain regions.

Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

Abstract: An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending in a second direction that intersects the first direction on the fin-type active region; a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween and extending in the second direction to be aligned with the insulating separation structure; a pair of source/drain regions located on the fin-type active region and spaced apart from each other with the insulating separation structure therebetween; and a jumper contact located over the insulating separation structure and connected between the pair of source/drain regions.