Abstract: Disclosed are a flash memory device and method of operation. The flash memory device includes a bottom memory cell array and a top memory cell array disposed over the bottom memory cell array. The bottom memory cell array includes a bottom semiconductor layer, a bottom well, and a plurality of bottom memory cell units. The top memory cell array includes a top semiconductor layer, a top well, and a plurality of top memory cell units. A well bias line is disposed over the top memory cell array and includes a bottom well bias line and a top well bias line, The bottom well bias line is electrically connected to the bottom well, and the top well bias line is electrically connected to the top well.

Abstract: A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

Abstract: A circuit board having a board body includes a via structure. The via structure includes a conductive connector passing through the board body and a conductive shield member surrounding at least a portion of the conductive connector. The shield member prevents distortion of a data signal applied to the conductive connector, and also intercepts electromagnetic waves generated by the conductive connector.

Abstract: There is provided a daily activity recognition system using sensors installed in required positions in a home to recognize daily activities of an old person, the system including: a radio frequency (RF) management unit receiving data measured by a plurality of sensors installed in required positions in a home, recognizing a corresponding sensor transmitting the received data, and converting the received data into a basic activity corresponding to the recognized sensor; a buffer management unit storing the basic activity received from the wireless processing manager in an internal buffer; and a daily activity recognition unit recognizing daily activities of an old person at each point in time previously set, based on the basic activity stored in the buffer. The daily activities of the old person are recognized and stored in a database, thereby providing various services related to the health of the old person.

Abstract: A circuit board having a board body includes a via structure. The via structure includes a conductive connector passing through the board body and a conductive shield member surrounding at least a portion of the conductive connector. The shield member prevents distortion of a data signal applied to the conductive connector, and also intercepts electromagnetic waves generated by the conductive connector.

Abstract: Disclosed are nonaqueous electrolyte additives, which can improve the safety of a battery upon overcharge of the battery without reducing the performance of the battery, as well as a nonaqueous electrolyte comprising the additives, and a lithium secondary battery comprising the nonaqueous electrolyte. More particularly, disclosed are a nonaqueous electrolyte comprising both fluorobiphenyl and fluorotoluene as additives, and a lithium secondary battery comprising the nonaqueous electrolyte.

Abstract: Disclosed is a lithium-containing metal composite oxide comprising paramagnetic and diamagnetic metals, which satisfies any one of the following conditions: (a) the ratio of intensity between a main peak of 0±10 ppm (Io PPm) and a main peak of 240±140 ppm (I240 pPm), Uoppm/124o PPm), is less than 0.117·Z wherein Z is the ratio of moles of the diamagnetic metal to moles of lithium; (b) the ratio of line width between the main peak of 0±10 ppm (Io PPm) and the main peak of 240+140 ppm (I24o PPm), (W24o PPm/WO ppm), is less than 21.45; and (c) both the conditions (a) and (b), the peaks being obtained according to the 7Li—NMR measurement conditions and means disclosed herein. Also, an electrode comprising the lithium-containing metal composite oxide, and an electrochemical device comprising the electrode are disclosed.

Abstract: Disclosed is a method for preparing a lithium-metal composite oxide, the method comprising the steps of: (a) mixing an aqueous solution of one or more transition metal-containing precursor compounds with an alkalifying agent and a lithium precursor compound to precipitate hydroxides of the transition metals; (b) mixing the mixture of step (a) with water under supercritical or subcritical conditions to synthesize a lithium-metal composite oxide, and drying the lithium-metal composite oxide; and (c) subjecting the dried lithium-metal composite oxide either to calcination or to granulation and then calcination. Also disclosed are an electrode comprising the lithium-metal composite oxide, and an electrochemical device comprising the electrode. In the disclosed invention, a lithium-metal composite oxide synthesized based on the prior supercritical hydrothermal synthesis method is subjected either to calcination or to granulation and then calcination.

Abstract: A MOS transistor that has a protruding portion with a favorable vertical profile and a protruded-shape channel that requires no additional photolithography process, and a method of fabricating the same are provided. A first mask that defines an isolation region of a substrate is overall etched to form a second mask with a smaller width than the first mask. Then, the substrate is etched to a predetermined depth while using the second mask as an etch mask, thereby forming the protruding portion. Without performing a photolithography process, the protruding portion has a favorable profile and the protruding height of an isolation layer is adjusted to be capable of appropriately performing ion implantation upon the protruding portion.

Abstract: A stacked memory includes at least two semiconductor layers each including a memory cell array. A transistor is formed in a peripheral circuit region of an uppermost semiconductor layer of the at least two semiconductor layers. The transistor is used to operate the memory cell array.

Abstract: The present invention relates to a plasma display apparatus, and more particularly, to a plasma display apparatus for preventing Electromagnetic Interference (EMI). The plasma display apparatus of the present invention comprises a plasma display panel comprising an electrode, and at least one of a first capacitor connected between a sustain voltage source for supplying a sustain voltage to the electrodes and a first ground voltage source, a second capacitor connected between a scan voltage source for supplying a scan voltage to the electrodes and a second ground voltage source, and a third capacitor connected between a set-up voltage source for supplying a set-up voltage to the electrodes and a third ground voltage source.

Abstract: A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.

Abstract: On embodiment of a contact structure may include a lower insulation layer on a lower substrate, an upper substrate on the lower insulation layer, a groove penetrating the upper substrate to extend into the lower insulation layer, the groove below an interface between the upper substrate and the lower insulation layer, an upper insulation layer in the groove, and a contact plug penetrating the upper insulation layer in the groove to extend into the lower insulation layer.

Abstract: Disclosed are a flash memory device and method of operation. The flash memory device includes a bottom memory cell array and a top memory cell array disposed over the bottom memory cell array. The bottom memory cell array includes a bottom semiconductor layer, a bottom well, and a plurality of bottom memory cell units. The top memory cell array includes a top semiconductor layer, a top well, and a plurality of top memory cell units. A well bias line is disposed over the top memory cell array and includes a bottom well bias line and a top well bias line, The bottom well bias line is electrically connected to the bottom well, and the top well bias line is electrically connected to the top well.

Abstract: Disclosed are a safety element for a battery, which is provided with material having a Metal-Insulator Transition (MIT) characteristic where resistance abruptly drops at or above a certain temperature, and a battery with such a safety element. This battery with an MIT safety element is turned into a stable discharged state when it is exposed to an elevated temperature or a battery temperature rises due to external impact, so that it can ensure its safety.

Abstract: A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.

Abstract: A NAND flash memory device includes a lower semiconductor layer and an upper semiconductor layer located over the lower semiconductor layer, a first drain region and a first source region located in the lower semiconductor layer, and a second drain region and a second source region located in the upper semiconductor layer. A first gate structure is located on the lower semiconductor layer, and a second gate structure is located on the upper semiconductor layer. A bit line is located over the upper semiconductor layer, and at least one bit line plug is connected between the bit line and the first drain region, where the at least one bit line plug extends through a drain throughhole located in the upper semiconductor layer.

Abstract: A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

Abstract: A circuit board having a board body includes a via structure. The via structure includes a conductive connector passing through the board body and a conductive shield member surrounding at least a portion of the conductive connector. The shield member prevents distortion of a data signal applied to the conductive connector, and also intercepts electromagnetic waves generated by the conductive connector.

Abstract: The present invention relates to a biological implantation material and method of preparing the same, which comprises the steps of: (i) treating a tissue derived from animal or human with alcohol; (ii) contacting the said tissue with an enzyme selected from the group consisting of dispase, DNAse, RNAse and pepsin in a solvent; (iii) treating the tissue obtained in step (ii) with alkaline solution; and (iv) treating the tissue obtained in step (iii) with acid solution.