Abstract: An adhesive composition for semiconductor devices, an adhesive film, and a dicing die bonding film, the adhesive composition including an elastomer resin, an epoxy resin, a curable phenolic resin, a curing accelerator, a silane coupling agent, and a filler, wherein the silane coupling agent includes an epoxy group-containing silane coupling agent and a transition metal scavenging functional group-containing silane coupling agent.

Abstract: A system on chip (SOC) include at least one slave device, a plurality of master devices, a plurality of service controllers and an interconnect device. The master devices generate requests to demand services from the slave device, respectively. The service controllers generate urgent information signals and priority information signals for each of the master devices. The interconnect device is coupled to the slave device and the master devices through respective channels. The interconnect device performs an arbitrating operation on the requests based on the priority information signals and controls request flows between the slave device and the master devices based on the urgent information signals.

Abstract: A power circuit for reducing a leakage power using a negative voltage is provided. The power circuit includes a current source including a transistor including a gate. The power circuit further includes a current source control circuit connected to the gate of the transistor, and configured to apply a positive voltage to the gate of the transistor if the current source is to operate in an active mode, and apply the negative voltage to the gate of the transistor if the current source is to operate in an inactive mode.

Abstract: A polarizing plate and an optical member, the polarizing plate including an adhesive layer, the adhesive layer being prepared from an adhesive composition including a (meth)acrylic copolymer, a crosslinking agent, and a tackifier, the tackifier including an acrylic modified petroleum resin represented by Formula 1: R?—CO—O—R??[Formula 1] wherein R? is a petroleum resin and R is a C1-C20 alkyl group or a C6-C50 aryl group.

Abstract: An asynchronous bridge includes a transmission unit and a receiving unit. The transmission unit receives a write valid signal and input data from a master circuit, outputs write addresses increment under control of the write valid signal, sequentially stores the input data in memory cells, as directed by write addresses, and then sequentially outputs the stored input data, as directed by read addresses. The receiving unit receives a read ready signal from a slave circuit, determines whether memory cells are valid, based on the write addresses and the read addresses, and then outputs a read valid signal and the input data, based on the determination.

Abstract: An asynchronous upsizing circuit in a data processing system. The asynchronous upsizing circuit includes an asynchronous packer and an asynchronous unpacker. The asynchronous packer includes a write buffer commonly used for an asynchronous bridge and for upsizing and for buffering a write channel data; and first and second asynchronous packing controllers controlling channel compaction according to first and second clocks, respectively, regarding the write channel data inputted/outputted to/from the write buffer during a burst write operation. The asynchronous unpacker includes a read buffer commonly used for an asynchronous bridge and for upsizing and for buffering a read channel data; and first and second asynchronous unpacking controllers controlling channel compaction according to the first and second clocks, respectively, regarding the read channel data inputted/outputted to/from the read buffer during a burst read operation.

Abstract: There is provided a method of manufacturing a multilayer ceramic capacitor including: laminating ceramic green sheets having internal electrodes printed thereon to form a ceramic laminated body; cutting the ceramic laminated body; applying slurry including a ceramic powder to the ceramic laminated body; and drying the slurry applied to the ceramic laminated body. According to an embodiment of the present invention, cracks generated in a manufacturing process of the multilayer ceramic capacitor may be removed, such that the multilayer ceramic capacitor may have excellent reliability.

Abstract: Address transforming methods are provided. The methods may include generating a power-up signal when a semiconductor memory device is powered-up. The methods may further include generating a randomized output signal in response to the power-up signal. The methods may additionally include transforming bits of a first address in response to the randomized output signal to generate a second address.

Abstract: There is provided multilayered ceramic electronic component having a 0603 size or less, the multilayered ceramic electronic component including: a ceramic body including a plurality of internal electrodes and dielectric layers disposed between the internal electrodes; and external electrodes disposed on outer surfaces of the ceramic body and electrically connected to the internal electrodes, wherein when a region in which the internal electrodes are overlapped is defined as an active region in a cross section of a central portion in a length direction of the ceramic body, taken in width and thickness directions thereof, the entire area of the cross section taken in the width and thickness directions is defined as At, and an area of the active region is defined as Aa, the following equation is satisfied: 65%?Aa/At?90%.

Abstract: There is provided a multilayer ceramic electronic component, including: a ceramic main body including a dielectric layer; and inner electrodes disposed to face each other within the ceramic main body, with the dielectric layer interposed therebetween, wherein, when an average thickness of the dielectric layer is td and an average thickness of the inner electrodes is te, 0.1 ?m?te?0.5 ?m and (td+te)/te?2.5 are satisfied, and when an average surface roughness on a virtual surface roughness center line of the inner electrode is Ra and an average roughness of ten points of the inner electrode is Rz, 5 nm?Ra?30 nm, 150 nm?Rz?td/2, and 8?Rz/Ra?20 are satisfied. The multilayer ceramic electronic component has excellent reliability by improving adhesion strength between the dielectric layer and the inner electrodes and withstand voltage characteristics.

Abstract: There are provided a ceramic electronic component and a method of manufacturing the same. The ceramic electronic component includes: a ceramic element; and an internal electrode layer formed within the ceramic element, having a thickness of 0.5 ?m or less, and including anon-electrode region formed therein, wherein an area ratio of the non-electrode region to an electrode region of the internal electrode layer, in a cross section of the internal electrode layer is between 0.1% and 10%, and the non-electrode region includes a ceramic component.

Abstract: A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.

Abstract: There are provided a conductive paste composition for an internal electrode and a multilayer ceramic electronic component including the same. The conductive paste composition includes: 100 moles of a metal powder; 0.5 to 4.0 moles of a ceramic powder; and 0.03 to 0.1 mole of a silica (SiO2) powder. The conductive paste composition can raise the sintering shrinkage temperature of the internal electrodes and improve the connectivity of the internal electrodes, and can improve the degree of densification of the dielectric layer, thereby improving withstand voltage characteristics, reliability, and dielectric characteristics.

Abstract: There are provided a conductive paste composition for internal electrodes and a multilayer ceramic electronic component including the same. The conductive paste composition includes: a metal powder; and a refractory metal oxide powder having a smaller average grain diameter than the metal powder and a higher melting point than the metal powder. The conductive paste composition can raise the sintering shrinkage temperature of the internal electrodes and improve the connectivity of the internal electrodes.

Abstract: There is provided a multilayered ceramic electronic component capable of securing capacitance by controlling electrode connectivity. The multilayered ceramic electronic component includes: a ceramic main body; and internal electrodes formed in the interior of the ceramic main body and having a central portion and a tapered portion becoming thinner from the central portion toward edges thereof, respectively, wherein the ratio of the area of the tapered portion to the overall area of the internal electrodes is 35% or less. A desired capacitance can be obtained by controlling an electrode connectivity even in the small high capacitance multilayered ceramic capacitor.

Abstract: Disclosed herein is a conductive paste composition. The conductive paste composition according to the exemplary embodiment of the present invention includes a conductive powder including nickel or a nickel alloy; a spherical particulate inhibitor including BaTiO3 powders; and a glass composition having Chemical Formula of aLi2O-bK2O-cCaO-dBaO-eB2O3-fSiO2, wherein a, b, c, d, e, and f satisfy a+b+c+d+e+f=100, 2?a?10, 2?b?10, 0?c?25, 0?d?25, 5?e?20, and 50?f?80.

Abstract: A conductive paste composition for an internal electrode, and a multilayer ceramic capacitor (MLCC) including the same are provided. The conductive paste composition for an internal electrode includes: 100 parts by weight of metal powder particles; and 0.1 to 10 parts by weight of carbon nano-tubes (CNTs). The conductive paste composition for an internal electrode may control sintering shrinkage of metal powder particles.

Abstract: The fuse circuit includes a first program unit, a second program unit and a sensing circuit. The first and second program units are programmed simultaneously. The first program unit is programmed in a program mode in response to a fuse program signal and outputs a first signal in a sensing mode, such that the first signal increases when the first program unit is programmed. The second program unit is programmed in the program mode in response to the program signal and outputs a second signal in the sensing mode, such that the second signal decreases when the second program unit is programmed. The sensing circuit generates a sensing output signal in response to the first and second signals, such that the sensing output signal indicates whether or not the program units are programmed.

Abstract: A system on chip (SoC) includes a first master, a slave, a bus switch transmitting a first command of the master and a first response of the slave, and a first priority controller connected between the first master and the bus switch The first priority controller measures at least one of first bandwidth and first latency based on the first command and the first response and adjusts the priority of the first command according to at least one of the measurement results.

Abstract: A system on chip includes a plurality of master devices, a plurality of slave devices that supply data in response to requests of the plurality of master devices and pointer update logic configured to process the requests from the plurality of master devices sequentially in a pipeline manner.