Abstract: An electronic device and a method for supporting a payment function are disclosed. The electronic device includes a communication module, at least one memory configured to store a payment application and payment information relating to the payment application, and a processor, wherein the memory stores instructions that, when executed, cause the processor to receive the payment information from an external device via the communication module and store the received payment information in the memory, receive a stop or deactivation request of the payment application and/or the payment information from the external device via the communication module, and in response to the request, stop or deactivate the payment application and/or the payment information.

Abstract: A leakage current-based delay circuit is provided, wherein the delay circuit may include a first transistor circuit and a second transistor circuit, each transistor circuit may include a p-type transistor, an n-type transistor, an n-node between a drain node of the p-type transistor and a gate node of the n-type transistor, and a p-node between a gate node of the p-type transistor and a drain node of the n-type transistor. The p-node of the second transistor circuit may be charged based on a power source voltage through the first transistor circuit during a first time interval of an input signal, and the n-node of the second transistor circuit may be discharged based on a ground voltage through the first transistor circuit during the first time interval.

Abstract: A system on chip (SoC) is present that includes a plurality of master interfaces, a plurality of slave interfaces, and an interface circuit which is connected between the plurality of master interfaces and the plurality of slave interfaces and includes a plurality of components. When a first master interface among the plurality of master interfaces and a first slave interface among the plurality of slave interfaces are paired, a first group of the components which forms a first signal path between the first master interface and the first slave interface among the plurality of components is enabled according to a control of the first master interface.

Abstract: A semiconductor memory device includes a memory cell array, a refresh control circuit, an address counter and an address converter. The memory cell array includes a plurality of memory cells. The refresh control circuit is configured to receive a refresh command and output m refresh control signals during one refresh cycle for refreshing all the memory cells of the semiconductor memory device. The address counter is configured to generate counting signals for refreshing memory cells in response to the m refresh control signals. The address converter is configured to receive the counting signals and output refresh addresses by converting the counting signals in response to a cycle select signal. The address converter is configured to output refresh addresses such that the number of m refresh control signals during one refresh cycle is variable.

Abstract: A system on chip (SOC) include at least one slave device, a plurality of master devices, a plurality of service controllers and an interconnect device. The master devices generate requests to demand services from the slave device, respectively. The service controllers generate urgent information signals and priority information signals for each of the master devices. The interconnect device is coupled to the slave device and the master devices through respective channels. The interconnect device performs an arbitrating operation on the requests based on the priority information signals and controls request flows between the slave device and the master devices based on the urgent information signals.

Abstract: A backbone channel transmits first through third channel packets among Advanced eXtensible Interface (AXI) 5 channel packets. The backbone channel is managed by dividing the backbone channel into a first sub-channel and a second sub-channel, transmitting the first channel packet through the first sub-channel, transmitting the second channel packet through the second sub-channel, and transmitting the third channel packet through both the first sub-channel and the second sub-channel.

Abstract: An electronic device for communicating in a network is provided. The electronic device includes a circuit board, a frame, a feeding structure formed on the circuit board, and an antenna unit disposed in a plane at a predetermined angle with respect to a surface of the circuit board. In addition, the antenna unit is disposed apart from the frame in electrical connection with the feeding structure.

Abstract: An adhesive film for polarizing plates has a K value of about 0.2 to about 0.5, as calculated by Equation 1. A polarizing plate includes the adhesive film for polarizing plates. An optical display includes the polarizing plate. The adhesive films for polarizing plates according to embodiments of the invention suppress light leakage due to dimensional changes in the polarizing plates at high temperature and/or high humidity.

Abstract: According to an embodiment of the present invention, provided is a touch detection device comprising: a plurality of sensor pads disposed to configure a plurality of columns for forming touch capacitance in a relationship with a touch generation means; and a plurality of signal wirings extending from each of the plurality of sensor pads and connected to a touch detection unit which detects touch generation on the basis of output signals from the plurality of sensor pads, wherein at least a part of the plurality of signal wirings extends through the gap between the plurality of sensor pads belonging to the same column.

Abstract: A semiconductor memory device includes a memory cell array, a refresh control circuit, an address counter and an address converter. The memory cell array includes a plurality of memory cells. The refresh control circuit is configured to receive a refresh command and output m refresh control signals during one refresh cycle for refreshing all the memory cells of the semiconductor memory device. The address counter is configured to generate counting signals for refreshing memory cells in response to the m refresh control signals. The address converter is configured to receive the counting signals and output refresh addresses by converting the counting signals in response to a cycle select signal. The address converter is configured to output refresh addresses such that the number of m refresh control signals during one refresh cycle is variable.

Abstract: A memory device comprises: a memory cell array comprising first and second word lines located adjacent to each other, a first memory cell connected to the first word line, and a second memory cell connected to the second word line and located adjacent to the first memory cell; and a word line voltage supplying unit that transitions a word line voltage of the first word line from a first word line voltage to a second word line voltage, in response to a first control signal. A transition control unit generates the first control signal for controlling a pulse of the word line voltage of the first word line in a transition period from the first word line voltage to the second word line voltage in such a way that a transition waveform profile from the first word line voltage to the second word line voltage is different from a transition waveform profile from the second word line voltage to the first word line voltage.

Abstract: An antenna of an electronic device is provided, which includes a radiator including at least part of a metal housing of the electronic device; a capacitor connected to the radiator; a feeding part connected to the radiator; and a ground part connected to the capacitor.

Abstract: A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.

Abstract: An asynchronous bridge includes a transmission unit and a receiving unit. The transmission unit receives a write valid signal and input data from a master circuit, outputs write addresses increment under control of the write valid signal, sequentially stores the input data in memory cells, as directed by write addresses, and then sequentially outputs the stored input data, as directed by read addresses. The receiving unit receives a read ready signal from a slave circuit, determines whether memory cells are valid, based on the write addresses and the read addresses, and then outputs a read valid signal and the input data, based on the determination.

Abstract: An ultra high-strength flux-cored arc welded joint having excellent impact toughness comprises: 0.01 wt % to 0.06 wt % of carbon (C), 0.1 wt % to 0.5 wt % of silicon (Si), 1.5 wt % to 3.0 wt % of manganese (Mn), 2.5 wt % to 3.5 wt % of nickel (Ni), 0.5 wt % to 1.0 wt % of molybdenum (Mo), 0.4 wt % to 1.0 wt % of copper (Cu), 0.4 wt % to 1.0 wt % of chromium (Cr), 0.01 wt % to 0.1 wt % of titanium (Ti), 0.003 wt % to 0.007 wt % of boron (B), 0.001 wt % to 0.006 wt % of nitrogen (N), 0.02 wt % (excluding 0) or less of phosphorus (P), 0.01 wt % (excluding 0) or less of sulfur (S), 0.03 wt % to 0.07 wt % of oxygen (O), and remaining iron (Fe) as well as unavoidable impurities.

Abstract: A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.

Abstract: A semiconductor memory device includes a sense amplifier circuit region including first wells disposed in a first direction, a driving circuit region including second wells disposed in a second direction, and a conjunction region disposed at an intersection region of the sense amplifier circuit region and the driving circuit region, a part of each of the first wells extending from the sense amplifier circuit region into the conjunction region, and the second wells being outside of the conjunction region.

Abstract: There are provided a ceramic electronic component and a method of manufacturing the same. The ceramic electronic component includes: a ceramic element; and an internal electrode layer formed within the ceramic element, having a thickness of 0.5 ?m or less, and including a non-electrode region formed therein, wherein an area ratio of the non-electrode region to an electrode region of the internal electrode layer, in a cross section of the internal electrode layer is between 0.1% and 10%, and the non-electrode region includes a ceramic component.

Abstract: A system interconnect is provided which includes a first channel configured to transmit a plurality of control signals based on a first clock, and a second channel configured to transmit a plurality of data signals which correspond to the control signals based on a second clock. The first channel and the second channel allows a predetermined range of out-of-orderness, and the predetermined range of the out-of-orderness indicates that an order of the control signals is different from an order of the data signals which correspond to the control signals.

Abstract: A semiconductor memory device includes a memory cell array, a refresh control circuit, an address counter and an address converter. The memory cell array includes a plurality of memory cells. The refresh control circuit is configured to receive a refresh command and output m refresh control signals during one refresh cycle for refreshing all the memory cells of the semiconductor memory device. The address counter is configured to generate counting signals for refreshing memory cells in response to the m refresh control signals. The address converter is configured to receive the counting signals and output refresh addresses by converting the counting signals in response to a cycle select signal. The address converter is configured to output refresh addresses such that the number of m refresh control signals during one refresh cycle is variable.