Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory block including a plurality of memory cells; a default refresh controller configured to receive a refresh command from a host, to generate a default refresh signal, and to control the memory cells to be refreshed; and a weak cell refresh controller configured to receive the default refresh signal, to generate a weak cell refresh signal, and to control a weak cell among the memory cells to be refreshed. The weak cell may be refreshed at least one more time during a refresh period during which all of the memory cells are refreshed by the default refresh controller. The semiconductor memory device performs at least one more refresh on a weak cell having a data retention time shorter than a refresh period apart from a normal default refresh, thereby preventing data loss.

Abstract: A semiconductor device may comprise a first bit line, a second bit line, a memory cell connected to the first bit line, a bit line sense amplifier circuit and a control circuit. The bit line sense amplifier circuit may be coupled to the memory cell. The bit line sense amplifier circuit may include a first inverter having an input node coupled to the first bit line and an output node coupled to the second bit line, and a second inverter having an input node coupled to the second bit line and an output node coupled to the first bit line. The control circuit may be configured to activate the first inverter without activating the second inverter during a first time period and to activate the first inverter and the second inverter at the same time during a second time period after the first time period.

Abstract: Provided is a backlight assembly including: a light source which generates and emits light; a light leakage preventing member including a first horizontal portion and a first vertical portion; a light guide plate including a light input surface and a light output surface; an optical sheet disposed on the light output surface of the light guide plate; and a bottom chassis configured to receive the light source, the light leakage preventing member and the light guide plate therein, in which the light source is disposed at a side of the light guide plate, the first vertical portion of the light leakage preventing member is attached to a rear surface of the light source, and the first horizontal portion is positioned above the light source to overlap a portion of the light output surface of the light guide plate.

Abstract: Disclosed is an optical sheet which is used in a liquid crystal display. The optical sheet is not readily damaged by external impact, and thus is easy to handle and can reduce failure rate, leading to a decrease in production cost and an increase in production efficiency. Also, it can prevent a decrease in brightness.

Abstract: A semiconductor device includes a substrate and a device isolation pattern extending from a surface of the substrate into the substrate. The device isolation pattern has an electrically negative property and a physically tensile property. The device isolation pattern delimits an active region of the substrate. A transistor is provided at the active region and has a channel region formed by part of the active region.

Abstract: A pulse shaping circuit is configured to shape a waveform of an edge of a signal applied to a switch of a power amplifier included in an on-off keying transmitter.

Abstract: A semiconductor memory device includes a memory cell array, a refresh control circuit, an address counter and an address converter. The memory cell array includes a plurality of memory cells. The refresh control circuit is configured to receive a refresh command and output m refresh control signals during one refresh cycle for refreshing all the memory cells of the semiconductor memory device. The address counter is configured to generate counting signals for refreshing memory cells in response to the m refresh control signals. The address converter is configured to receive the counting signals and output refresh addresses by converting the counting signals in response to a cycle select signal. The address converter is configured to output refresh addresses such that the number of m refresh control signals during one refresh cycle is variable.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory block including a plurality of memory cells; a default refresh controller configured to receive a refresh command from a host, to generate a default refresh signal, and to control the memory cells to be refreshed; and a weak cell refresh controller configured to receive the default refresh signal, to generate a weak cell refresh signal, and to control a weak cell among the memory cells to be refreshed. The weak cell may be refreshed at least one more time during a refresh period during which all of the memory cells are refreshed by the default refresh controller. The semiconductor memory device performs at least one more refresh on a weak cell having a data retention time shorter than a refresh period apart from a normal default refresh, thereby preventing data loss.

Abstract: A system-on-chip bus system and an operating method of the same are provided. The bus system includes a master device, a slave device and an interconnector coupled between the master device and the slave device. The interconnector includes a synchronization/compaction block to control traffic provided from a master device to a slave device. When a write request traffic and a corresponding write data traffic are all provided from the master device, the synchronization/compaction block may transfer the two traffics to the slave device.

Abstract: A system on chip (SoC) includes a first master, a slave, a bus switch transmitting a first command of the master and a first response of the slave, and a first priority controller connected between the first master and the bus switch The first priority controller measures at least one of first bandwidth and first latency based on the first command and the first response and adjusts the priority of the first command according to at least one of the measurement results.

Abstract: A memory device comprises: a memory cell array comprising first and second word lines located adjacent to each other, a first memory cell connected to the first word line, and a second memory cell connected to the second word line and located adjacent to the first memory cell; and a word line voltage supplying unit that transitions a word line voltage of the first word line from a first word line voltage to a second word line voltage, in response to a first control signal. A transition control unit generates the first control signal for controlling a pulse of the word line voltage of the first word line in a transition period from the first word line voltage to the second word line voltage in such a way that a transition waveform profile from the first word line voltage to the second word line voltage is different from a transition waveform profile from the second word line voltage to the first word line voltage.

Abstract: A vehicle data collecting apparatus includes a file receiver for receiving an extensible markup language (XML) script file, an XML parser for extracting data format information for each vehicle model and network by parsing the XML script file received. A controller is configured to control a data collector so as to collect vehicle data base on the data format information extracted and the data collector collects the vehicle data through the controller. The vehicle data collecting system may flexibly collect vehicle data regardless of a data format which depends on a vehicle model and vehicle network by collecting the vehicle data based on the extensible markup language (XML) script file generated by a managing server.

Abstract: A method of repairing a word line of a memory device includes receiving a row address, comparing a received row address with a row address of a defective cell, enabling a normal word line and a redundant word line, which correspond to the row address, according to a result of the row address comparison, receiving a column address, comparing a received column address with a column address of the defective cell, and performing a memory access operation on one of the normal word line and the redundant word line according to a result of the column address comparison.

Abstract: A polarizing plate and an optical member, the polarizing plate including an adhesive layer, the adhesive layer being prepared from an adhesive composition including a (meth)acrylic copolymer, a crosslinking agent, and a tackifier, the tackifier including an acrylic modified petroleum resin represented by Formula 1: R?—CO—O—R??[Formula 1] wherein R? is a petroleum resin and R is a C1-C20 alkyl group or a C6-C50 aryl group.

Abstract: There is provided a multilayer ceramic electronic component, including: a ceramic main body including a dielectric layer; and inner electrodes disposed to face each other within the ceramic main body, with the dielectric layer interposed therebetween, wherein, when an average thickness of the dielectric layer is td and an average thickness of the inner electrodes is te, 0.1 ?m?te?0.5 ?m and (td+te)/te?2.5 are satisfied, and when an average surface roughness on a virtual surface roughness center line of the inner electrode is Ra and an average roughness of ten points of the inner electrode is Rz, 5 nm?Ra?30 nm, 150 nm?Rz?td/2, and 8?Rz/Ra?20 are satisfied. The multilayer ceramic electronic component has excellent reliability by improving adhesion strength between the dielectric layer and the inner electrodes and withstand voltage characteristics.

Abstract: A vehicle information providing apparatus provides vehicle information based on a message policy script including a message ID containing data required by each of multiple services, location and length of data in a message, and an interval at which the data is required by each of the services. The apparatus provides messages by filtering the message ID or the interval, or creates and provides a new message containing necessary data only.

Abstract: A method of controlling a refresh operation for a memory device is disclosed. The method includes storing a first row address corresponding to a first row of a memory cell array, storing one or more second row addresses corresponding to one or more second rows of the memory cell array, the one or more second row addresses corresponding to the first row address, sequentially generating row addresses as a refresh row address during a first refresh interval, for each generated row address, when a generated row address identical to one of the one or more second row addresses is detected, stopping the generation of row addresses and sequentially outputting the one second row address and the first row address as the refresh row address, restarting the generation of the row addresses as the refresh row address after outputting the one second row address and the first row address.

Abstract: A memory refresh method includes selecting at least one bank from among N banks of a memory device, and activating K word lines from among a plurality of word lines included in the at least one bank during one of L refresh cycles of a refresh period. Each of the N banks comprises M word lines, N, K and M are each a natural number greater than or equal to two, L is a natural number less than or equal to M, and K is equal to M*N/L.

Abstract: An interface device includes a request queue and a request queue manager. The request queue includes multiple elements configured to receive corresponding requests from at least one master device and to indicate whether the corresponding requests are included using corresponding occupying bits. The request queue manager is configured to manage the request queue at least based on the occupying bits.

Abstract: A system-on-a-chip semiconductor device comprises a first master device configured to issue a request having a transaction ID, a plurality of slave devices configured to provide data in response to the request, and an interconnector configured to include a slave interface for providing the request to one or more master interfaces and for supplying response data to the first master device based on operation characteristics of the first master. An arbitration method of an interconnector transferring a plurality of response data provided from a plurality of slave devices to a master device comprises selecting one of a plurality of arbitration modes based on operation characteristics of the master device; and transferring the response data in the order determined by transfer priority corresponding to the selected arbitration mode.