Patents by Inventor Chun-An Hsieh

Chun-An Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6150235
    Abstract: A method for forming shallow trench isolation (STI) structures on a semiconductor substrate is disclosed. First a semiconductor substrate with a first area and a second area adjacent to the first area is provided. A mask layer is formed on the substrate, and is etched to expose portions of the substrate. A first photoresist is formed to cover the second area for exposing the first area. A first implanting procedure is performed with a titled angle to form first doping areas on the substrate encroaching into portions of the substrate covered by the first photoresist. The first photoresist is removed. A second photoresist is formed on the substrate to cover the first area for exposing the second area. And a second implanting procedure is done with a titled angle to form second doping areas on the substrate encroaching into portions of the substrate covered by the second photoresist. The second photoresist is removed.
    Type: Grant
    Filed: January 24, 2000
    Date of Patent: November 21, 2000
    Assignee: Worldwide Semiconductor Manufacturing Corp.
    Inventors: Yih-Yuh Doong, Sung-Chun Hsieh, Tsu-Bin Shen, Ching-Hsiang Hsu
  • Patent number: 6096645
    Abstract: A method of forming a CVD nitride (e.g., titanium nitride) film on a substrate. The as-deposited nitride film is treated by a plasma of a high power density (preferably between approximately 200 W and 300 W) for a prolonged duration of time (preferably between approximately 32 s and 52 s) to reduce the tendency of the resistance and thickness of the as-deposited film to change because of either time of exposure to atmosphere or subsequent processing steps.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: August 1, 2000
    Assignee: Mosel Vitelic, Inc.
    Inventors: Yung-Tsun Lo, Hui-lun Chen, Wen-Yu Ho, Sung-chun Hsieh, Feng-hsien Chao
  • Patent number: 6022800
    Abstract: A method of reducing tungsten plug loss in processes for fabrication for silicon-based semiconductor devices that include a tungsten plug in a high aspect ratio contact hole. The invention provides a barrier layer prepared by first forming a conformal layer of titanium nitride by chemical vapor deposition. Afterward, another film of titanium nitride is supplied by plasma vapor deposition. The barrier layer comprises at least these two films, and tungsten is then deposited to at least fill the high aspect ratio film-coated contact hole. Upon removal of excess tungsten as by wet etch back, the tungsten plug remains essentially intact, and any plug loss is insignificant in comparison with the prior art.
    Type: Grant
    Filed: April 29, 1998
    Date of Patent: February 8, 2000
    Assignee: Worldwide Semiconductor Manufacturing Corporation
    Inventors: Wen-Yu Ho, Sen-Nan Lee, Sung Chun Hsieh, Hui-Lun Chen
  • Patent number: 5966626
    Abstract: The present invention provides a method for stabilizing the crystal structure of a silicon substrate after an ion implantation process including the step of exposing the substrate to a temperature not higher than 200.degree. C. for a time period of not less than 10 seconds, and preferably to a temperature between about 100.degree. C. and about 200.degree. C. for a time period of between about 10 seconds and about 10,000 seconds.
    Type: Grant
    Filed: November 7, 1996
    Date of Patent: October 12, 1999
    Assignee: Mosel Vitelic, Inc.
    Inventors: Yung-Tsun Lo, Cheng-Hsun Tsai, Wen-Yu Ho, Jung-Chun Hsieh