Patents by Inventor Chun-An Wei

Chun-An Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11923396
    Abstract: An integrated circuit includes a photodetector. The photodetector includes one or more dielectric structures positioned in a trench in a semiconductor substrate. The photodetector includes a photosensitive material positioned in the trench and covering the one or more dielectric structures. A dielectric layer covers the photosensitive material. The photosensitive material has an index of refraction that is greater than the indices of refraction of the dielectric structures and the dielectric layer.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Wei Hsu, Tsai-Hao Hung, Chung-Yu Lin, Ying-Hsun Chen
  • Patent number: 11923199
    Abstract: Aspects of the disclosure provide a method. The method includes forming a structure over a substrate, and forming a spacer layer on the structure, wherein the spacer layer has a recess. The method includes forming a mask layer over the spacer layer and in the recess, the mask layer including a first layer, a second layer and a third layer. The method includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer to form an opening to expose the recess of the spacer layer, wherein the opening in the second layer has a first width; and. The method includes removing the second layer using a wet etchant, wherein the opening in the third layer has a second width, and the second with is greater than the first width.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Chia Chen, Wan Hsuan Hsu, Chia-Wei Wu, Neng-Jye Yang, Chun-Li Chou
  • Publication number: 20240071818
    Abstract: A semiconductor device and method of fabricating the same include a substrate, a first epitaxial layer, a first protection layer, and a contact etching stop layer. The substrate includes a PMOS transistor region, and the first epitaxial layer is disposed on the substrate, within the PMOS transistor region. The first protection layer is disposed on the first epitaxial layer, covering surfaces of the first epitaxial layer. The contact etching stop layer is disposed on the first protection layer and the substrate, wherein a portion of the first protection layer is exposed from the contact etching stop layer.
    Type: Application
    Filed: September 22, 2022
    Publication date: February 29, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: I-Wei Chi, Te-Chang Hsu, Yao-Jhan Wang, Meng-Yun Wu, Chun-Jen Huang
  • Publication number: 20240069618
    Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.
    Type: Application
    Filed: April 27, 2023
    Publication date: February 29, 2024
    Inventors: Wen Che CHUNG, Hui Chuan LO, Hao-Hsuan LIN, Chun TSAO, Jun-Fu CHEN, Ming-Hung YAO, Jia-Wei ZHANG, Kuan-Lun CHEN, Ting-Chao LIN, Cheng-Yen LIN, Chunyen LAI
  • Publication number: 20240069425
    Abstract: An illumination system including two light source modules, two light guiding modules, a first reflector, and a light homogenization element is provided. The two light guiding modules are respectively disposed on transmission paths of light beams generated by the two light source modules to generate two guiding light beams. One of the guiding light beams is reflected to the light homogenization element by the first reflector. The other of the guiding light beams is directly transmitted to the light homogenization element. The guiding light beams are emitted from the light homogenization element and form an illumination light beam. A projection apparatus is also provided.
    Type: Application
    Filed: August 24, 2023
    Publication date: February 29, 2024
    Applicant: Coretronic Corporation
    Inventors: Chun-Hsin Lu, Jen-Wei Kuo, Wen-Chieh Chung
  • Publication number: 20240070809
    Abstract: A method can include receiving a low-resolution (LR) image, extracting a first feature embedding from the LR image, performing a first upsampling to the LR image by a first upsampling factor to generate a upsampled image, receiving a LR coordinate of a pixel within the LR image and a first cell size of the LR coordinate, generating a first residual image based on the first feature embedding, the LR coordinate, and the first cell size of the LR coordinate using a local implicit image function, and generating a first high-resolution (HR) image by combining the first residual image and the upsampled image via element-wise addition.
    Type: Application
    Filed: April 12, 2023
    Publication date: February 29, 2024
    Applicants: MEDIATEK INC., National Tsing Hua University
    Inventors: Yu-Syuan XU, Hao-Wei CHEN, Chun-Yi LEE
  • Publication number: 20240073378
    Abstract: A projection apparatus including a light source module, an eccentric-collimating lens, a prism lens group, a light valve and a projection lens is provided. The light source module is configured to provide an illumination light beam. The eccentric-collimating lens is disposed between the light sources and the light valve on a transmission path of the illumination light beam. The light valve is configured to convert the illumination light beam into an image light beam. The projection lens is configured to project the image light beam out of the projection apparatus. A first included angle between a first transmission direction of the illumination light beam incident on the eccentric-collimating lens and a central axis of the eccentric-collimating lens is greater than 0. The first transmission direction and a second transmission direction of the image beam exiting from the light valve are perpendicular to each other.
    Type: Application
    Filed: August 24, 2023
    Publication date: February 29, 2024
    Applicant: Coretronic Corporation
    Inventors: Chun-Hsin Lu, Jen-Wei Kuo, Wen-Chieh Chung
  • Publication number: 20240071981
    Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.
    Type: Application
    Filed: November 1, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Yen Chang, Chih-Wei Lin, Hao-Yi Tsai, Kuo-Lung Pan, Chun-Cheng Lin, Tin-Hao Kuo, Yu-Chia Lai, Chih-Hsuan Tai
  • Publication number: 20240069069
    Abstract: A probe pin cleaning pad including a foam layer, a cleaning layer, and a polishing layer is provided. The cleaning layer is disposed between the foam layer and the polishing layer. A cleaning method for a probe pin is also provided.
    Type: Application
    Filed: November 10, 2023
    Publication date: February 29, 2024
    Applicant: Alliance Material Co., Ltd.
    Inventors: Chun-Fa Chen, Yu-Hsuen Lee, Ching-Wen Hsu, Chao-Hsuan Yang, Ting-Wei Lin
  • Patent number: 11917772
    Abstract: A power supply with a separable communication module includes a casing with a port; a main board placed in the casing and having a power conversion circuit; a sub-board electrically connected to the power conversion circuit and provided with at least one first connector; and a communication module. The power conversion circuit has at least one electrical connection terminal. A first interface of the first connector faces the port. The communication module includes a first circuit board and a communication circuit disposed on the first circuit board, the first circuit board has an electrical connection part electrically connected to the communication circuit, the electrical connection part has a first state of connecting with the first interface, and a second state of detaching from the first interface.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: February 27, 2024
    Assignee: COTEK ELECTRONIC IND. CO., LTD.
    Inventors: Chun-Wei Wu, Ta-Chang Wei, Chung-Liang Tsai, Shou-Cheng Yeh
  • Publication number: 20240064647
    Abstract: A modem chip, a communication device using the same and a method for dynamic controlling the same are provided. The method for dynamic controlling the modem chip includes the following steps. At least one traffic type factor or at least one channel condition factor is estimated. A cell-specific reference signal (CRS) reception mode is decided according to the traffic type factor or the channel condition factor. At least one hardware parameter is set according to the CRS reception mode to receive a plurality of cell-specific reference signals fully or partially.
    Type: Application
    Filed: August 15, 2023
    Publication date: February 22, 2024
    Inventors: Da-Hong HE, Chun-Wei SU
  • Publication number: 20240063839
    Abstract: A method for dynamically controlling a radio frequency circuit, a modem chip and a communication device are provided. The method for dynamically controlling the radio frequency circuit includes the following steps. At least one operation information is obtained. The operation information includes a software information, a hardware information and a firmware information. A plurality of working modes of the radio frequency circuit are switched to fit the operation information.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 22, 2024
    Inventors: Chun-Wei SU, Wei-Yi WANG, Yuan-Hwui CHUNG, Tz-Yuan SHIU
  • Publication number: 20240055295
    Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.
    Type: Application
    Filed: October 29, 2023
    Publication date: February 15, 2024
    Inventors: CHUN HAO LIAO, CHU FU CHEN, CHUN-WEI HSU, CHIA-CHENG PAO
  • Publication number: 20240055998
    Abstract: A photovoltaic inverter includes a casing, at least one circuit board located in the casing, a current sensor located on the at least one circuit board, an arc detector located on the at least one circuit board, a self-test coil located on the at least one circuit board, and at least one direct current input terminal located on the casing and connected to the at least one circuit board, wherein the self-test coil is configured to deliver a test signal to be sensed by the arc detector, and the direct current input terminal is configured to deliver a direct current through the arc detector, wherein the current sensor is configured to detect a magnitude of the direct current passing through the direct current input terminal.
    Type: Application
    Filed: June 5, 2023
    Publication date: February 15, 2024
    Inventors: Chun-Wei WU, Hung-Chuan LIN
  • Publication number: 20240053195
    Abstract: An ambient light sensor includes a substrate, a metasurface disposed on the substrate, and an aperture layer disposed on the substrate. The metasurface includes a plurality of nanostructures and a filling layer laterally surrounding the plurality of nanostructures. The aperture layer laterally separates the metasurface into a plurality of sub-meta groups.
    Type: Application
    Filed: March 29, 2023
    Publication date: February 15, 2024
    Inventors: Shih-Liang KU, Zi-Han LIAO, Chun-Wei HUANG
  • Patent number: 11902940
    Abstract: Methods and apparatuses for handling device-to-device feedback transmission in a wireless communication system are disclosed herein. In one method, a first device receives a configuration for operating in a network scheduling mode for acquiring sidelink resources. The first device receives a sidelink control information with a report request from a second device. The first device triggers or is triggered to transmit a report to the second device in response to the report request. If the first device has no available sidelink resource for transmitting the report, the first device triggers a scheduling request. The first device transmits a signaling of the scheduling request to the network. The first device receives a sidelink grant from the network. The first device utilizes sidelink resource(s) indicated by the sidelink grant to transmit the report to the second device.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: February 13, 2024
    Assignee: Asustek Computer Inc.
    Inventors: Ming-Che Li, Chun-Wei Huang, Yi-Hsuan Kung, Li-Chih Tseng
  • Publication number: 20240047460
    Abstract: A semiconductor device includes a first buried layer and a second buried layer both have a first conductivity type and are disposed in a substrate, where the second buried layer is disposed on the first buried layer. A first well region has the first conductivity type and is disposed above the second buried layer. A second well region has a second conductivity type and is adjacent to the first well region. A deep trench isolation structure is disposed in the substrate and surrounds the first and second well regions, where the bottom surface of the deep trench isolation structure is lower than the bottom surface of the first buried layer. A source region is disposed in the second well region. A drain region is disposed in the first well region. A gate electrode is disposed on the first and second well regions.
    Type: Application
    Filed: August 3, 2022
    Publication date: February 8, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chih-Cherng Liao, Chung-Ren Lao, Hsing-Chao Liu, Chun-Wei Li, Hsueh-Chun Liao
  • Publication number: 20240047345
    Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.
    Type: Application
    Filed: October 19, 2023
    Publication date: February 8, 2024
    Inventors: CHUN-WEI CHANG, HSUAN-MING HUANG, JIAN-HONG LIN, MING-HONG HSIEH, MINGNI CHANG, MING-YIH WANG
  • Publication number: 20240048324
    Abstract: In an example, a device, with a configuration of a sidelink resource pool comprising sidelink reference signal resources, determines candidate frequency resources of sidelink control channel in a slot in the sidelink resource pool. The candidate frequency resources are determined based on one or more parameters, one or more indexes and/or one or more identities associated with a plurality of candidate sidelink reference signal resources in the slot. The device performs monitoring on the candidate frequency resources. The device receives a sidelink control information (SCI) using a first frequency resource of the sidelink control channel. The candidate frequency resources include the first frequency resource of the sidelink control channel. The device measures a sidelink reference signal on a first sidelink reference signal resource in the slot.
    Type: Application
    Filed: July 28, 2023
    Publication date: February 8, 2024
    Inventors: MING-CHE LI, Chun-Wei Huang
  • Publication number: 20240047936
    Abstract: The present invention relates to a new electronic component package and its manufacturing method, especially the package of an optoelectronic component. The package comprises an electronically conductive base, an electronically conductive cap, and at least one electronic component. The base has an upper surface, a lower surface, and at least one through hole sealed with a conducting feedthrough surrounded by a ring of insulating material. The electronic component is fixed on the upper surface of the base and is electrically connected to the conducting feedthroughs and/or the base. The base and the cap are sealed by welding.
    Type: Application
    Filed: August 6, 2023
    Publication date: February 8, 2024
    Inventor: CHUN-WEI MI