Patents by Inventor Chun Chang

Chun Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220247479
    Abstract: A method for deploying an electromagnetic wave guiding structure includes a communication dead zone analysis step and an improvement measure determination step. In the former step, a frequency band in use and an electromagnetic wave signal strength threshold value are preset, and a processing module creates an electromagnetic map for the electromagnetic wave intensity over an area in the frequency band in use based on an electronic map of the area, wherein the electromagnetic map shows a communication dead zone. In the latter step, the processing module obtains an existing electromagnetic wave path according to the electromagnetic map and infers from the existing electromagnetic wave path the installation position and type of at least one electromagnetic wave guiding structure assembly suitable for use to guide the electromagnetic wave to the communication dead zone and ensure that the coverage ratio of the electromagnetic wave in the area reaches a threshold value.
    Type: Application
    Filed: July 12, 2021
    Publication date: August 4, 2022
    Inventors: SHENG-FUH CHANG, CHIA-CHAN CHANG, SHIH-CHENG LIN, YUAN-CHUN LIN
  • Publication number: 20220243715
    Abstract: A thin gas transportation device is provided and includes a shell, a check valve and a gas pump. The shell includes a shell surface, an accommodation slot and an outlet slot. The accommodation slot is recessed from the shell surface and includes an accommodation bottom surface. The outlet slot is recessed from the accommodation bottom surface. The check valve is disposed within the accommodation slot and includes a barrier plate and a valve plate. The barrier plate is disposed on the accommodation bottom surface and covers the outlet slot. The barrier plate includes a first surface, a second surface, a protruding part and a plurality of perforations. The protruding part is protruding from the second surface and located at the outlet slot. The valve plate is coupled to the second surface, and the protruding part abuts against the valve part and seals the valve hole.
    Type: Application
    Filed: January 27, 2022
    Publication date: August 4, 2022
    Applicant: Microjet Technology Co., Ltd.
    Inventors: Hao-Jan Mou, Chung-Wei Kao, Shih-Chang Chen, Jyun-Yi Jhang, Yung-Lung Han, Chi-Feng Huang, Chun-Yi Kuo
  • Publication number: 20220244507
    Abstract: A plastic light-folding element includes an incident surface, an exit surface, at least one reflective surface, at least one connecting surface and at least one gate vestige structure. The incident surface is configured to lead an imaging light enter the plastic light-folding element. The exit surface is configured to lead the imaging light exit the plastic light-folding element. The reflective surface is configured to fold the imaging light. The connecting surface is connected to the incident surface, the exit surface and the reflective surface. The gate vestige structure is disposed on the connecting surface. At least one of the incident surface, the exit surface and the reflective surface includes an optical portion and an arc step structure, the arc step structure is disposed on a periphery of the optical portion, and an arc is formed by the arc step structure centered on the optical portion.
    Type: Application
    Filed: January 14, 2022
    Publication date: August 4, 2022
    Inventors: Pei-Chi CHANG, Wei-Chun LO, Po-Lun HSU, Lin-An CHANG, Ming-Ta CHOU
  • Patent number: 11404631
    Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: August 2, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Yi-Syun Chou, Ko-Wei Lin, Pei-Hsun Kao, Wei Chen, Chia-Fu Cheng, Chun-Yao Yang, Chia-Chang Hsu
  • Patent number: 11404274
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over a first portion of the fin structure, and an epitaxial region formed in a second portion of the fin structure. The epitaxial region can include a first semiconductor layer and an n-type second semiconductor layer formed over the first semiconductor layer. A lattice constant of the first semiconductor layer can be greater than that of the second semiconductor layer.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Chun Chang, Guan-Jie Shen
  • Patent number: 11404418
    Abstract: A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Chun Liao, Chun-Sheng Liang, Shu-Hui Wang, Shih-Hsun Chang, Yi-Jen Chen
  • Patent number: 11404348
    Abstract: A semiconductor package carrier board, a method for fabricating the same, and an electronic package having the same are provided. The method includes forming on a circuit structure a graphene layer that acts as an insulation heat dissipating layer. Since the heat conductivity of the graphene layer is far greater than the heat conductivity of ink (about 0.4 W/m·k), which is used as solder resist, the heat of the semiconductor package carrier board can be conducted quickly, and thus can avoid the problem that the heat will be accumulated on the semiconductor package carrier board.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: August 2, 2022
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu, Wen-Chang Chen
  • Publication number: 20220238991
    Abstract: An electromagnetic wave transmission structure adapted to cause convergence of an electromagnetic wave includes a substrate and a transmission unit provided on the substrate and including an annular metal plate. The annular metal plate has a weighted average inner radius and a weighted average outer radius each related to the wavelength of the electromagnetic wave, the distance between the electromagnetic wave transmission structure and a focal point defined as the point of convergence of the electromagnetic wave, and the distance between the source of the electromagnetic wave and the focal point. The plural inner and outer radii of the annular metal plate have the same trend of variation. Each inner or outer radius corresponds to a weight related to the reference included angle formed between the inner or outer radius and a reference axis.
    Type: Application
    Filed: April 9, 2021
    Publication date: July 28, 2022
    Inventors: SHENG-FUH CHANG, CHIA-CHAN CHANG, SHIH-CHENG LIN, YUAN-CHUN LIN
  • Publication number: 20220238414
    Abstract: A thermal conductive structure and an electronic device are provided. The thermal conductive structure includes a thermal conductive metal layer and a structural layer. The structural layer is disposed on the thermal conductive metal layer. The structural layer is a stacked structure formed by a graphene layer and a ceramic material layer, or the structural layer is a graphene-mixed ceramic material layer. The thermal conductive structure can quickly conduct the heat energy generated by the heat source to the outside, thereby improving the heat dissipation performance of the electronic device.
    Type: Application
    Filed: December 3, 2021
    Publication date: July 28, 2022
    Inventors: Ming-Hsiang He, Chun-Kai Huang, Han-Chang Huang
  • Publication number: 20220240418
    Abstract: A thermal conductive structure and an electronic device are provided. The thermal conductive structure includes a thermal conductive metal layer, a first carbon nanotube layer, a first thermal conductive adhesive layer, and a ceramic protective layer. The first carbon nanotube layer is disposed on a first surface of the thermal conductive metal layer and includes a plurality of first carbon nanotubes. The first thermal conductive adhesive layer is disposed at the first carbon nanotube layer, wherein the material of the first thermal conductive adhesive layer fills in the gaps of the first carbon nanotubes. The ceramic protective layer is disposed at one side of the first carbon nanotube layer away from the thermal conductive metal layer. The thermal conductive structure can quickly conduct the heat generated by the heat source to the outside, and improve the heat dissipation performance of the electronic device.
    Type: Application
    Filed: December 3, 2021
    Publication date: July 28, 2022
    Inventors: MING-HSIANG HE, CHUN-KAI HUANG, HAN-CHANG HUANG
  • Publication number: 20220238572
    Abstract: A method includes etching a semiconductor substrate to form a trench, filling a dielectric layer into the trench, with a void being formed in the trench and between opposite portions of the dielectric layer, etching the dielectric layer to reveal the void, forming a diffusion barrier layer on the dielectric layer, and forming a high-reflectivity metal layer on the diffusion barrier layer. The high-reflectivity metal layer has a portion extending into the trench. A remaining portion of the void is enclosed by the high-reflectivity metal layer.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Inventors: Ming-Chi Wu, Chun-Chieh Fang, Bo-Chang Su, Chien Nan Tu, Yu-Lung Yeh, Kun-Yu Lin, Shih-Shiung Chen
  • Patent number: 11398557
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first well, a second well, an isolation structure, a first field plate, a gate structure, a drain structure, and a source structure. The first well and the second well adjoin each other. The first well and the second well are disposed in the substrate. The isolation structure is disposed on the first well. The first field plate is disposed on the isolation structure. The gate structure crosses the first well and the second well, and an opening is defined between the first field plate and the gate structure to expose an edge of the isolation structure adjacent to the gate structure. The drain structure is disposed in the first well. The source structure is disposed in the second well.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: July 26, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yi-Ching Chung, Jui-Chun Chang, Fu-Chun Tseng, Yu-Ping Ho
  • Patent number: 11398467
    Abstract: A method for forming a semiconductor device includes forming a first guard ring around at least one transistor over a substrate. The method further includes forming a second guard ring around the first guard ring, wherein the second guard ring directly contacts the first guard ring. The method further includes forming an isolation structure between the first guard ring and the second guard ring. The method further includes forming a first doped region adjacent to the first guard ring, the first doped region having a first dopant type. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having a second dopant type.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: July 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Song Sheu, Jian-Hsing Lee, Yu-Chang Jong, Chun-Chien Tsai
  • Patent number: 11398444
    Abstract: Electrical devices, semiconductor packages and methods of forming the same are provided. One of the electrical devices includes a substrate, a conductive pad, a conductive pillar and a solder region. The substrate has a surface. The conductive pad is disposed on the surface of the substrate. The conductive pillar is disposed on and electrically connected to the conductive pad, wherein a top surface of the conductive pillar is inclined with respect to the surface of the substrate. The solder region is disposed on the top surface of the conductive pillar.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: July 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chiang-Jui Chu, Ching-Wen Hsiao, Hao-Chun Liu, Ming-Da Cheng, Young-Hwa Wu, Tao-Sheng Chang
  • Patent number: 11398421
    Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: July 26, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chun-Che Lee, Ming-Chiang Lee, Yuan-Chang Su, Tien-Szu Chen, Chih-Cheng Lee, You-Lung Yen
  • Publication number: 20220229109
    Abstract: A test system is disclosed. The test system includes a tester, a first voltage stabilization circuit, and a device under test (DUT). The tester generates a first operational voltage and a control signal. The first voltage stabilization circuit transmits a second operational voltage, associated with the first operational voltage, to a socket board. The DUT operates with the second operational voltage received through the socket board. The first voltage stabilization circuit is further configured to control, according to the control signal, the second operational voltage to have a first voltage level when the DUT is operating.
    Type: Application
    Filed: January 21, 2021
    Publication date: July 21, 2022
    Inventors: Yu-Wei TSENG, Chih-Ming CHANG, Wan-Chun FANG, Jui-Chung HSU, Chun-Hsi LI
  • Publication number: 20220231158
    Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure, which has an upper fin structure made of SiGe and a bottom fin structure made of a different material than the upper fin structure, is formed, a cover layer is formed over the fin structure, a thermal operation is performed on the fin structure covered by the cover layer, and a source/drain epitaxial layer is formed in a source/drain region of the upper fin structure. The thermal operation changes a germanium distribution in the upper fin structure.
    Type: Application
    Filed: April 4, 2022
    Publication date: July 21, 2022
    Inventors: Hsiao-Chun CHANG, Guan-Jie SHEN
  • Publication number: 20220230689
    Abstract: An electrically erasable programmable read only memory (EEPROM) includes a substrate, bit lines, a row of erase gate and a row of floating gates. The bit lines are defined in the substrate to extend in a first direction. The row of erase gate having a wave shape is disposed across the bit lines. The row of floating gates having staggered islands is disposed parallel to the row of erase gate. A method of forming said electrically erasable programmable read only memory (EEPROM) is also provided.
    Type: Application
    Filed: January 18, 2021
    Publication date: July 21, 2022
    Inventors: Yi-Ning Peng, Hsueh-Chun Hsiao, Tzu-Yun Chang
  • Publication number: 20220230674
    Abstract: An operation method for a memory device is provided. The operation method includes: increasing an adjacent word line voltage to a first adjacent word line voltage during a pre-turn on period; and increasing the adjacent word line voltage from the first adjacent word line voltage to a second adjacent word line voltage after the pre-turn on period is finished; wherein the first adjacent word line voltage is lower than the second adjacent word line voltage; the adjacent word line voltage is applied to at least one adjacent word line, and the at least one adjacent word line is adjacent to a selected word line.
    Type: Application
    Filed: January 21, 2021
    Publication date: July 21, 2022
    Inventors: Chih-Chieh CHENG, Chun-Chang LU, Wen-Jer TSAI
  • Publication number: 20220231956
    Abstract: A data flow classification device includes a forwarding circuit and a configuring circuit. The forwarding circuit looks the classification of an input flow up in a lookup table according to the information of the input flow, tags the packets of the input flow with the classification, and outputs the packets to a buffer circuit; but if the classification is not found in the lookup table, the forwarding circuit tags the packets with a predetermined classification, outputs the packets to the buffer circuit, and adds the information of the input flow to the lookup table. The configuring circuit determines a flow threshold according to a queue length of the buffer circuit and a target length, learns the traffic of multiple flows from the lookup table, determines the classifications of the multiple flows according to the comparison between the traffic and the flow threshold, and stores these classifications in the lookup table.
    Type: Application
    Filed: September 3, 2021
    Publication date: July 21, 2022
    Inventors: KUO-CHENG LU, MIN-CHANG WEI, CHUN-MING LIU, KUANG-YU YEN