Abstract: A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, the metal gate structure being surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first dielectric layer over the recessed metal gate structure; forming an etch stop layer (ESL) over the first dielectric layer and the ILD layer; forming a second dielectric layer over the ESL; performing a first dry etch process to form an opening that extends through the second dielectric layer, through the ESL, and into the first dielectric layer; after the first dry etch process, performing a wet etch process to clean the opening; and after the wet etch process, performing a second dry etch process to extend the opening through the first dielectric layer.

Abstract: An object detection model training apparatus, method and non-transitory computer readable storage medium thereof are provided. The apparatus performs a first object detection on a plurality of training images to generate a piece of first label information corresponding to each of the training images by a first teacher model. The apparatus trains a student model based on the training images and the first label information. The apparatus performs a second object detection on the training images to generate a piece of second label information corresponding to each of the training images by a second teacher model. The apparatus trains the student model based on the training images and the second label information.

Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a main branch extending along a first direction on the substrate and a sub-branch extending along a second direction adjacent to the main branch. The semiconductor device also includes a first doped region overlapping the main branch and the sub-branch according to a top view and a second doped region overlapping the first doped region.

Abstract: A battery pack assembly method includes compressing at least one cell stack, inserting the at least one cell stack into a cell-receiving opening of an enclosure structure, and pushing at least one cell of the at least one cell stack out of the enclosure structure using a pusher. Another traction battery pack assembly method includes moving a cell stack into an enclosure structure from a compression fixture that compresses the cell stack. The cell stack includes a plurality of battery cells. After the moving, the method compresses the cell stack using the enclosure structure. The method then includes establishing electrical connections between the battery cells of the cell stack, and testing the electrical connections prior to securing a busbar to the cell stack.

Abstract: A polymer structure and applications thereof are provided. The polymer structure includes a substrate and a light shielding layer covering at least a portion of the surface of the substrate, wherein the substrate includes a first polymer, the light shielding layer comprises a second polymer which includes a structural unit derived from a first ultraviolet absorber, the light shielding layer has a thickness of 1 ?m to 200 ?m, and the first ultraviolet absorber is a polyfunctional reactive ultraviolet absorber.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, from a network node, a network assistant information (NAI) message identifying a set of characteristics of a network connection. The UE may communicate with the network node using a communication configuration associated with the set of characteristics of the network connection. Numerous other aspects are described.

Abstract: The disclosed technology relates to a network agent for reporting to a network policy system. A network agent includes an agent enforcer and an agent controller. The agent enforcer is configured to implementing network policies on the system, access data associated with the implementation of the network policies on the system, and transmit, via an interprocess communication, the data to the agent controller. The agent controller is configured to generate a report including the data and transmit the report to a network policy system.

Abstract: A display assembly includes a three-dimensional display cover defining an internal volume. The three-dimensional display cover includes a central portion and a peripheral portion. The peripheral portion extends around a periphery of the internal volume. The display assembly includes a first display and a second display. The first display is disposed within the internal volume of the three-dimensional display cover and is visible through the central portion of the three-dimensional display cover. The second display is disposed within the internal volume of the three-dimensional display cover and extends around at least a portion of a periphery of the first display. Furthermore, the second display is visible through the peripheral portion of the three-dimensional display cover.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over a first portion of the fin structure, and an epitaxial region formed in a second portion of the fin structure. The epitaxial region can include a first semiconductor layer and an n-type second semiconductor layer formed over the first semiconductor layer. A lattice constant of the first semiconductor layer can be greater than that of the second semiconductor layer.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a metal gate stack over a substrate and an epitaxial structure over the substrate. The semiconductor device structure also includes a conductive contact electrically connected to the epitaxial structure. A topmost surface of the metal gate stack is vertically disposed between a topmost surface of the conductive contact and a bottommost surface of the conductive contact. The semiconductor device structure further includes a first conductive via electrically connected to the metal gate stack. The topmost surface of the conductive contact is vertically disposed between a topmost surface of the first conductive via and a bottommost surface of the first conductive via. In addition, the semiconductor device structure includes a second conductive via electrically connected to the conductive contact.

Abstract: An electronic device includes a first electrode; a second electrode on the first electrode; a semiconductor layer between the first electrode and the second electrode; and a first self-assembled monolayer between the first electrode and the semiconductor layer. The first self-assembled monolayer includes a compound represented by Formula (1) below: X - R 2 - Si ? ( OR 1 ) 3 , ( 1 ) wherein in Formula (1), R1 are each independently a C1-C5 alkyl group; R2 is a C1-C20 alkylene group; and X is an electron withdrawing group.

Abstract: Disclosed is a control circuit of an atmospheric plasma generating device, comprising: a power supply suppling power to the control circuit, a switching element, a first set of resistors, a second set of resistors, a set of Zener diodes, a set of transistors electrically coupled to the switching element, the set of Zener diodes, the first set of resistors and the second set of resistors. The control circuit further includes a capacitor, an inductor, and a set of diodes electrically coupled to the first set of resistors or the second set of resistors.

Abstract: Embodiments provide a dielectric inter block disposed in a metallic region of a conductive line or source/drain contact. A first and second conductive structure over the metallic region may extend into the metallic region on either side of the inter block. The inter block can prevent etchant or cleaning solution from contacting an interface between the first conductive structure and the metallic region.

Abstract: Semiconductor devices and methods of manufacturing the same are provided in which memory cells are manufactured with a double sided word line structure. In embodiments a first word line is located on a first side of the memory cells and a second word line is located on a second side of the memory cells opposite the first side.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: An ovonic threshold switch (OTS) selector and a memory device including the OTS selector is provided. The OTS selector includes a switching layer formed of a GeCTe compound further doped with one or both of nitrogen and silicon, and exhibits improved thermal stability and electrical performance.

Abstract: A battery module includes a housing, an outer cover, cell assemblies, a circuit board, connecting wires and conductive assemblies. The housing includes a top plate and two side plates respectively connected with opposite sides thereof. The side plates respectively includes hollow windows arranged along a direction. The outer cover covers the two side plates and forms a chamber with the housing. Cell assemblies are arranged in the chamber along the direction. The circuit board is arranged on the top plate. Connecting wires are electrically connected with the circuit board and cell assemblies. Conductive assemblies correspond to the positions of hollow windows and are electrically connected with two adjacent cell assemblies among cell assemblies. An abnormal or damaged cell assembly can be replaced by disassembling the battery module, while the normal cell assemblies keep in use, meeting the needs in recycling and repairing.

Abstract: An example method includes detecting, using sensors, packets throughout a datacenter. The sensors can then send packet logs to various collectors which can then identify and summarize data flows in the datacenter. The collectors can then send flow logs to an analytics module which can identify the status of the datacenter and detect an attack.

Abstract: The disclosure relates to methods for treating biliary tract cancer (BTC) using an anti-PD-L1 antibody in combination with chemotherapy.

Abstract: The present disclosure provides a system and method for enabling cableless connections within a server system. The server system comprises a motherboard (MB) module, a power distribution board (PDB) module, power supply unit (PSU) modules, network interface controller (NIC) modules, fan modules, graphic process unit (GPU) modules, and a hyperscale GPU accelerator (HGX) platform. These components of the server system are interconnected by a plurality of circuit boards. The plurality of circuit boards includes, but is not limited to, a main board, linking boards (BDs), a PDB, a fan board, a power linking board, peripheral-component-interconnect-express (PCIe) expander boards, a plurality of NVLink bridges, and HGX base boards.