Abstract: A heating device includes a first capacitor, a first switch, a second switch, a second capacitor, a third capacitor, a coil and a controller. The first and second switch are coupled in series at a first node, and are coupled with the first capacitor in parallel. The second capacitor is coupled to the first switch. The third capacitor is coupled to the second switch, and is coupled to the second capacitor at a second node. The coil is coupled between the first and the second node. The controller outputs a first and a second control signal to the first switch and the second switch, respectively. After the heating device received a voltage and a starting command, the controller outputs the first and the second control signal to turn on or off the first and the second switch respectively. The duty cycle of the first signal is lower than 50%.

Abstract: A wafer defect inspection system is disclosed, and comprises a line light source, a camera and a processor, wherein the processor is configured to control the line light source to provide an inspection light to be incident on a wafer, wherein an included angle between the inspection light and the surface of the wafer ranges from 450 to 90°. After incidence on the wafer, the inspection light travels inside the wafer according to the principle of total reflection, and when encountering a crack, part of the inspection light exits from the surface of the wafer through the crack. Moreover, the processor controls the camera to obtain a wafer image containing at least one defect feature, and after processing the wafer image into an inspection wafer image, compares the wafer image with a reference wafer image, so as to know the at least one defect feature.

Abstract: Hydrofluoric acid waste streams from semiconductor device manufacturing processes are collected and converted to cryolite utilizing disclosed systems and processes. The systems and processes are able to utilize hydrofluoric acid waste streams from multiple different sources. The systems and processes utilizing control delivery of reactant so that the produced cyrolite has low impurity levels and meets industry standards.

Abstract: A p-GaN high-electron-mobility transistor, includes a substrate, a channel layer stacked on the substrate, a supply layer stacked on the channel layer, a first doped layer stacked on the supply layer, a second doped layer stacked on the first doped layer, and a third doped layer stacked on the second doped layer. A doping concentration of the first doped layer and the doping concentration of the third doped layer are lower than a doping concentration of the second doped layer. A gate is located on the third doped layer, and a source and a drain are electrically connected to the channel layer and the supply layer, respectively.

Abstract: Existing spatial transcriptomics technologies require dead tissues and are not compatible with live cell cultures. The present disclosure provides materials and methods for sequencing a single cell from a cell culture sample and obtaining morphologic or phenotypic measurements and information by combining sequencing approaches and spatial hashing (e.g., barcoding) at a single cell level.

Abstract: The present disclosure relates to pharmaceutical composition for the treatment of joint pain. The composition contains a lipid mixture comprising one or more phospholipids; and an effective amount of a therapeutic agent or a pharmaceutically acceptable salt thereof, where the total amount of phospholipids in said composition is about 20 mM to about 150 mM, optionally 70 mM to 110 mM. Also provided is the use of the pharmaceutical composition in the treatment of joint pain by articular injection.

Abstract: A point estimate value for an individual is computed using a Bayesian neural network model (BNN) by training a first BNN model that computes a weight mean value, a weight standard deviation value, a bias mean value, and a bias standard deviation value for each neuron of a plurality of neurons using observations. A plurality of BNN models is instantiated using the first BNN model. Instantiating each BNN model of the plurality of BNN models includes computing, for each neuron, a weight value using the weight mean value, the weight standard deviation value, and a weight random draw and a bias value using the bias mean value, the bias standard deviation value, and a bias random draw. Each instantiated BNN model is executed with the observations to compute a statistical parameter value for each observation vector of the observations. The point estimate value is computed from the statistical parameter value.

Abstract: A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.

Abstract: A semiconductor structure is provided in the present invention, including a substrate, a deep N-well formed in the substrate, a first well formed in the deep N-well, a first gate formed on the first well, a first source and a first drain formed respectively at two sides of the first gate in the first well, a first doped region formed in the first well, and a metal interconnect electrically connected with the first source and the first doped region, wherein an area of the deep N-well multiplied by a first parameter is a first factor, an area of the first gate multiplied by a second parameter is a second factor, and an area of the metal interconnect divided by a sum of the first factor and the second factor is less than a specification value.

Abstract: A tape measure includes a housing having an interior surface with a post mount protruding therefrom, and a post having a shaft extending from a keyed shape. The post and the post mount are configured such that the post is slid laterally along the interior surface until the post mount is received in the keyed shape. The keyed shape is configured to prevent rotation of the shaft relative to the housing once the keyed shape is received in the post mount.

Abstract: A seismically suspended isolation device is installed in a suspended configuration at a fixed end and comprises a first support module, a second support module, a first displacement suppressing module and a second displacement suppressing module. The first support module includes a first fixing element, a first moving element, and at least one first roller. The first roller is disposed between the first fixing element and the first moving element. The second support module includes a second fixing element, a second moving element, and at least one second roller. The second roller is disposed between the second fixing element and the second moving element. The first support module and the second support module are stacked together in an orthogonal manner, so that the seismically suspended isolation device generates motion in the first direction and the second direction when the seismically suspended isolation device subjected to an external force.

Abstract: An immersion cooling system includes a cooling tank and a filtration system. The cooling tank is configured to accommodate a liquid coolant and an electronic device immersed in the liquid coolant. The filtration system includes a pipeline, a pump, a filter and a cooling device. The pipeline is in fluid communication with the cooling tank. The pump is disposed in the pipeline and is configured to drive the liquid coolant to flow through the pipeline. The filter is disposed in the pipeline and is configured to filter the liquid coolant. The cooling device is connected to the pipeline and is configured to cool the liquid coolant. The pipeline has an inlet connected to the cooling tank. The cooling device is located between the pump and the inlet of the pipeline.

Abstract: A semiconductor device includes a substrate provided with an electronic device, an interlayer dielectric (ILD) layer formed over the electronic device, a wiring pattern formed on the ILD layer and a contact formed in the ILD layer and physically and electrically connecting the wiring pattern to a conductive region of the electronic device. An insulating liner layer is provided on sidewalls of the contact between the contact and the ILD layer. A height of the insulating liner layer measured from a top of the conductive region of the electronic device is less than 90% of a height of the contact measured between the top of the conductive region and a level of an interface between the ILD layer and the wiring pattern.

Abstract: An immersion cooling system includes a tank, a first condenser, an enclosure, a second condenser and a connecting pipe. The tank has a first space. The first space is configured to accommodate a cooling liquid for at least one electronic equipment to immerse therein. The first condenser is disposed inside the tank. The enclosure is disposed outside the tank. The enclosure forms a second space together with the tank. The second condenser is disposed in the second space. The connecting pipe includes a first end and a second end opposite to the first end. The first end is connected with the second condenser. The second end is communicated with the first space.

Abstract: Disclosed is a control circuit of an atmospheric plasma generating device, comprising: a power supply suppling power to the control circuit, a switching element, a first set of resistors, a second set of resistors, a set of Zener diodes, a set of transistors electrically coupled to the switching element, the set of Zener diodes, the first set of resistors and the second set of resistors. The control circuit further includes a capacitor, an inductor, and a set of diodes electrically coupled to the first set of resistors or the second set of resistors.

Abstract: A method for laser processing wafer surface comprises following steps of: providing a wafer; performing profile scanning a top surface of the wafer by a scanning device to obtain a profile distribution of the top surface of the wafer; and performing laser processing on the wafer from the top surface of the wafer by a laser apparatus with a fluence integration distribution to form a laser-processed wafer, wherein the fluence integration distribution is related to the profile distribution of the top surface of the wafer.

Abstract: A data storage device is adaptively adjusted according to the sensed temperature. The data storage device has a first clock generator and a second clock generator, respectively generating a first clock and a second clock, which are selected by a controller to operate a nonvolatile memory. In response to the sensed temperature not exceeding a first threshold temperature, the controller selects the first clock to operate the non-volatile memory. In response to the sensed temperature exceeding the first threshold temperature, the controller alternately selects the first clock and the second clock to operate the non-volatile memory.

Abstract: A light-emitting-diode driver structure applicable to driving a display panel and operation method thereof are provided. The LED driver structure includes at least one LED driving group, and the LED driving group is composed of a plurality of LED driving circuits which are serially connected in cascade. Each LED driving circuit of the LED driving group receives a data input signal in common. Upon receiving control signals, output signals are generated to drive the display panel. The multi-point driving circuit scheme can be fully or partially applied in the driver structure as required. In addition, a plurality of enable signals can be further adopted to activate each LED driving circuit, for avoiding the FIFO register used in the prior arts. By employing the disclosed technical contents, the present invention is effective in reducing both redundant power waste and circuit layout area of a conventional LED driver.

Abstract: A PCI-E bus standard compliant multifunctional interface board includes a substrate, a PCI-E connector, a storage device, a non-storage device and a signal dispatch device. The PCI-E connector is provided on the substrate and is configured to be electrically connected to a host. The storage device and the non-storage device are provided on the substrate. The signal dispatch device is provided on the substrate and includes: an upstream port, a downstream port and an I/O controller. The upstream port is electrically connected to the PCI-E connector. The downstream port is electrically connected to the storage device and/or the non-storage device. The I/O controller is electrically connected to the upstream port and the downstream port to control an electrical connection relationship between the host and the storage device and/or the non-storage device.

Abstract: A tape measure includes a housing having an interior surface with a post mount protruding therefrom, and a post having a shaft extending from a keyed shape. The post and the post mount are configured such that the post is slid laterally along the interior surface until the post mount is received in the keyed shape. The keyed shape is configured to prevent rotation of the shaft relative to the housing once the keyed shape is received in the post mount.