Abstract: A method for performing storage space management of a memory device with aid of dynamic block configuration includes: configuring at least one portion of blocks among a plurality of blocks to be multiple first blocks in a first region and multiple second blocks in a second region according to a first reserved block threshold; combining the multiple first blocks into a set of first superblocks in the first region; and combining at least one portion of second blocks among the multiple second blocks into a set of second superblocks in the second region, wherein the first reserved block threshold is less than a minimum non-damaged block count among respective non-damaged block counts of a plurality planes, for a memory controller to increase available storage capacity by increasing a ratio of a size of the second region to a size of the first region.

Abstract: The present invention relates to a method for preparing etelcalcetide hydrochloride (etelcalcetide HCL). A first peptide is de-protected and cleaved from a solid support by a first solution system, for obtaining a second peptide, followed by coupling an activated L-Cys-OH to the second peptide in the second solution system for forming a TFA salt of etelcalcetide that is not or hardly dissolved in the second solution system. After purification by column chromatography, the TFA salt of etelcalcetide can be converted to etelcalcetide HCL using a third solution system that excludes hydrogen chloride during a real-time monitoring salt exchange step. The present method provides a simplified process and the etelcalcetide HCL with high purity and yield, for being advantageously applied in mass production of etelcalcetide HCL.

Abstract: A treatment model trained to compute an estimated treatment variable value for each observation vector of a plurality of observation vectors is executed. Each observation vector includes covariate variable values, a treatment variable value, and an outcome variable value. An outcome model trained to compute an estimated outcome value for each observation vector using the treatment variable value for each observation vector is executed. A standard error value associated with the outcome model is computed using a first variance value computed using the treatment variable value of the plurality of observation vectors, using a second variance value computed using the treatment variable value and the estimated treatment variable value of the plurality of observation vectors, and using a third variance value computed using the estimated outcome value of the plurality of observation vectors. The standard error value is output.

Abstract: Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.

Abstract: The present disclosure describes semiconductor devices and methods for forming the same. A semiconductor device includes nanostructures over a substrate and a source/drain region in contact with the nanostructures. The source/drain region is doped with a first-type dopant. The semiconductor device also includes a counter-doped structure in contact with the substrate and the source/drain region. The counter-doped structure is doped with a second-type dopant opposite to the first-type dopant.

Abstract: A semiconductor device includes source/drain contacts, a gate structure, a gate dielectric cap, an etch stop layer, and a gate contact. The source/drain contacts are over a substrate. The gate structure is laterally between the source/drain contacts. The gate dielectric cap is over the gate structure and in contact with the source/drain contacts. The etch stop layer is over the source/drain contacts and the gate dielectric cap. The etch stop layer has an oxidized region directly above the gate dielectric cap. The gate contact extends through the etch stop layer and the gate dielectric cap to the gate structure. The gate contact and the oxidized region of the etch stop layer form an interface perpendicular to the substrate.

Abstract: Disclosed are methods, devices and the non-transitory computer storage media of matching clinical trials. The present disclosure provides a method of matching clinical trials. The method comprises: obtaining a first data set from a pathology report; obtaining a second data set of a clinical trial; determining whether the first data set and the second data set are matched with respect to a first set of fields; determining a relevance value between the first data set and the second data set with respect to a second set of fields when the first data set and the second data set are matched with respect to the first set of fields; and determining the clinical trial as recommended when the relevance value exceeds a threshold.

Abstract: An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The ring resonator is over the substrate and overlaps with the transistor. The ring resonator includes a conductive loop and an impedance matching element. The conductive loop includes a loop portion having two first parts and a second part and two feeding lines. Each of the first parts of the loop portion is between the second part of the loop portion and one of the feeding lines, and a tunnel barrier of the transistor is closer to the second part than to the feeding lines. The impedance matching element is closer to the feeding lines than to the second part.

Abstract: The present disclosure relates to a force measuring device (1) comprising a spring module (2), and an electronic module (3), detachably mechanically connected to the spring module. The spring module comprises a test head (21) defining an outer surface of the device, a spring seat (23), and a spring (24) arranged between the test head and the spring seat, with a first end (24a) of the spring engaging the test head and a second end (24b) of the spring engaging the spring seat. The electronic module comprises a force sensor (31) arranged in physical contact with the spring seat.

Abstract: A printing device and the ribbon mounting mechanism thereof are disclosed. The ribbon mounting mechanism is used for mounting a first ribbon comprising a first core and a second ribbon comprising a second core having a diameter smaller than that of the first core. The ribbon mounting mechanism includes a first shaft supporting the first core of the first ribbon; a second shaft supporting the second core of the second ribbon, wherein the second shaft and the first shaft are concentrically disposed; a torque generator comprising a third shaft; a first gear set connecting the first shaft and the third shaft, and torque generated by the torque generator is transmitted to the first shaft through the first gear set; and a second gear set connecting the second shaft and the third shaft, and torque generated by the torque generator is transmitted to the second shaft through the second gear set.

Abstract: Embodiments include a contact structure and method of forming the same where the contact structure is deliberately positioned near the end of a metallic line. An opening is formed in an insulating structure positioned over the metallic line and then the opening is extended into the metallic line by an etching process. In the etching process, the line end forces etchant to concentrate back away from the line end, causing lateral etching of the extended opening. A subsequent contact is formed in the opening and enlarged opening.

Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a semiconductor device, a polysilicon isolation structure, and a first and second insulator liner. The semiconductor device is disposed on a frontside of a substrate. The polysilicon isolation structure continuously surrounds the semiconductor device and extends from the frontside of the substrate towards a backside of the substrate. The first insulator liner and second insulator liner respectively surround a first outermost sidewall and a second outermost sidewall of the polysilicon isolation structure. The substrate includes a monocrystalline facet arranged between the first and second insulator liners. A top of the monocrystalline facet is above bottommost surfaces of the polysilicon isolation structure, the first insulator liner, and the second insulator liner.

Abstract: The present disclosure provides an immersion cooling system for a server cabinet including a plurality of server boxes, a cooling tank and a plurality of liquid connecting pipes. Each server box includes an electronic device immersed in the cooling liquid, and the electronic device generates a thermal energy so that part of the cooling liquid evaporates into a hot vapor. The cooling tank is connected to the plurality of server boxes and includes a condenser and a storage part. The condenser is connected to each server box and condenses the hot vapor to form the cooling liquid. The storage part storages the cooling liquid from the condenser. Two ends of the liquid connecting pipe is connected to the storage part and the server box respectively. The cooling liquid in the storage part and the cooling liquid of each server box are maintained in a same liquid level.

Abstract: A semiconductor device includes a substrate provided with an electronic device, an interlayer dielectric (ILD) layer formed over the electronic device, a wiring pattern formed on the ILD layer and a contact formed in the ILD layer and physically and electrically connecting the wiring pattern to a conductive region of the electronic device. An insulating liner layer is provided on sidewalls of the contact between the contact and the ILD layer. A height of the insulating liner layer measured from a top of the conductive region of the electronic device is less than 90% of a height of the contact measured between the top of the conductive region and a level of an interface between the ILD layer and the wiring pattern.

Abstract: Systems, methods, and computer-readable media for managing compromised sensors in multi-tiered virtualized environments. In some embodiments, a system can receive, from a first capturing agent deployed in a virtualization layer of a first device, data reports generated based on traffic captured by the first capturing agent. The system can also receive, from a second capturing agent deployed in a hardware layer of a second device, data reports generated based on traffic captured by the second capturing agent. Based on the data reports, the system can determine characteristics of the traffic captured by the first capturing agent and the second capturing agent. The system can then compare the characteristics to determine a multi-layer difference in traffic characteristics. Based on the multi-layer difference in traffic characteristics, the system can determine that the first capturing agent or the second capturing agent is in a faulty state.

Abstract: An adjustment method of screen brightness comprises the following steps. Step (a): obtaining a relationship between a brightness and refresh rate of the screen. Step (b): adjusting the screen to a highest refresh rate and displaying an image at a first brightness. Step (c): decreasing the first brightness by a unit brightness value and variably displaying the image between a first refresh rate and a second refresh rate. Step (d): determining whether the image does not flicker; if not, repeating step (c). Step (e): calculating a first brightness difference between a decreased brightness of the screen and a brightness corresponding to a lowest refresh rate when the image does not flicker. Step (f): determining whether the first brightness difference is less than a screen flicker threshold; if yes, decreasing the first brightness corresponding to the highest refresh rate to obtain an adjusted brightness corresponding to the highest refresh rate.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a semiconductor device, a polysilicon isolation structure, and a first and second insulator liner. The semiconductor device is disposed on a frontside of a substrate. The polysilicon isolation structure continuously surrounds the semiconductor device and extends from the frontside of the substrate towards a backside of the substrate. The first insulator liner and second insulator liner respectively surround a first outermost sidewall and a second outermost sidewall of the polysilicon isolation structure. The substrate includes a monocrystalline facet arranged between the first and second insulator liners. A top of the monocrystalline facet is above bottommost surfaces of the polysilicon isolation structure, the first insulator liner, and the second insulator liner.

Abstract: GAAFET threshold voltages are tuned by introducing dopants into a channel region. In a GAAFET that has a stacked channel structure, dopants can be introduced into multiple channels by first doping nano-structured layers adjacent to the channels. Then, by an anneal operation, dopants can be driven, from surfaces of the doped layers into the channels, to achieve a graduated dopant concentration profile. Following the anneal operation and after the dopants are diffused into the channels, depleted doped layers can be replaced with a gate structure to provide radial control of current in the surface-doped channels.