Patents by Inventor Chun-Chen Yeh

Chun-Chen Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Nanowire semiconductor device including lateral-etch barrier region
    Patent number: 9455317
    Abstract: A semiconductor device includes a semiconductor-on-insulator wafer having a buried oxide layer. The buried oxide layer includes therein opposing etch barrier regions and a gate region between the etch barrier regions. The semiconductor device further includes at least one nanowire having a channel portion interposed between opposing source/drain portions. The channel portion is suspended in the gate region. A gate electrode is formed in the gate region, and completely surrounds all surfaces of the suspended nanowire. The buried oxide layer comprises a first electrical insulating material, and the etch barrier regions comprising a second electrical insulating material different from the first electrical insulating material.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: September 27, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • METHOD OF FORMING EPITAXIAL BUFFER LAYER FOR FINFET SOURCE AND DRAIN JUNCTION LEAKAGE REDUCTION
    Publication number: 20160276463
    Abstract: A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.
    Type: Application
    Filed: June 1, 2016
    Publication date: September 22, 2016
    Inventors: DECHAO GUO, SHOGO MOCHIZUKI, ANDREAS SCHOLZE, CHUN-CHEN YEH
  • FINFET INCLUDING TUNABLE FIN HEIGHT AND TUNABLE FIN WIDTH RATIO
    Publication number: 20160276348
    Abstract: A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.
    Type: Application
    Filed: May 31, 2016
    Publication date: September 22, 2016
    Inventors: Xiuyu Cai, Qing Liu, Ruilong Xie, Chun-chen Yeh
  • Lithography process monitoring of local interconnect continuity
    Patent number: 9443775
    Abstract: Disclosed is a novel system and method to form local interconnects in a continuity test structure. The method begins with a first set of transistor gate lines and a second set of transistor gate lines are formed. Next, a first group of two or more local interconnect lines landing on transistor gates and formed substantially perpendicular to the first set of transistor gate lines and electrically coupled therewith is formed using a first lithography pass. A second group of two or more local interconnect lines landing and formed substantially perpendicular to the second set of transistor gate lines and electrically coupled therewith is formed during second lithography pass. For some technologies, a third set of transistor gate lines is formed along with a third group using a third lithography pass.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: September 13, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hyun-Jin Cho, Tenko Yamashita, Chun-chen Yeh, Hui Zang
  • SEMICONDUCTOR DEVICES HAVING FINS, AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING FINS
    Publication number: 20160260741
    Abstract: In forming a finFET, a selective nitridation process is used during spacer formation on the gate to support a finer fin pitch than could be achieved using traditional spacer deposition processes. The spacer formation may also allow precise control over formation of source and drain junctions.
    Type: Application
    Filed: May 16, 2016
    Publication date: September 8, 2016
    Applicants: STMicroelectronics, Inc., International Business Machines Corporation, GlobalFoundries Inc
    Inventors: Qing Liu, Chun-Chen Yeh, Ruilong Xie, Xiuyu Cai, Kejia Wang
  • Semiconductor device including merged-unmerged work function metal and variable fin pitch
    Patent number: 9437499
    Abstract: A method of varying a threshold voltage of a semiconductor device includes forming plural first semiconductor fins atop a substrate and which are separated from one another according to a first fin pitch to define first fin trenches having a first width. At least one second semiconductor fin is formed atop the substrate and is separated from the plural first semiconductor fins by a second fin pitch to define second fin trenches having a second width. The method further includes forming a work function metal layer in the first and second fin trenches. The second trenches have a first cavity formed therein such that at least one second semiconductor fin has a different concentration of work function metal layer with respect to the first plural semiconductor fins so as to vary the threshold voltage of the at least one second semiconductor fin with respect to the first plural semiconductor fins.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: September 6, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-chen Yeh
  • Replacement metal gate FinFET
    Patent number: 9437436
    Abstract: A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: September 6, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hemanth Jagannathan, Sanjay C. Mehta, Junli Wang, Chun-Chen Yeh, Stefan Schmitz
  • FINFET HAVING CONTROLLED DIELECTRIC REGION HEIGHT
    Publication number: 20160254178
    Abstract: Embodiments are directed to a method of forming a dielectric region of a fin-type field effect transistor (FinFET). The method includes forming at least one fin, and forming a dielectric region adjacent a lower portion of the at least one fin, wherein the dielectric region includes a top surface. The method further includes forming a blocking layer on the top surface of the dielectric region, wherein the blocking layer is configured to prevent at least one subsequent FinFET fabrication operation from impacting the top surface of the dielectric region.
    Type: Application
    Filed: February 23, 2015
    Publication date: September 1, 2016
    Inventors: Dechao Guo, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Method for making a semiconductor device with sidewall spacers for confining epitaxial growth
    Patent number: 9431540
    Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: August 30, 2016
    Assignees: STMICROELECTRONICS, INC., GLOBALFOUNDRIES Inc., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qing Liu, Ruilong Xie, Xiuyu Cai, Chun-chen Yeh
  • Stress memorization technique for strain coupling enhancement in bulk finFET device
    Patent number: 9431521
    Abstract: A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: August 30, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Chun-Chen Yeh
  • Shallow trench isolation for end fin variation control
    Patent number: 9412643
    Abstract: A method of fabricating a fin field effect transistor (FinFET) device and the device are described. The method includes forming a deep STI region adjacent to a first side of an end fin among a plurality of fins and lining the deep STI region, including the first side of the end fin, with a passivation layer. The method also includes depositing an STI oxide into the deep STI region, the passivation layer separating the STI oxide and the first side of the end fin, etching back the passivation layer separating the STI oxide and the first side of the end fin to a specified depth to create a gap, and depositing gate material, the gate material covering the gap.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: August 9, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Semiconductor device with thinned channel region and related methods
    Patent number: 9412820
    Abstract: A method for making a semiconductor device may include forming a dummy gate above a semiconductor layer on an insulating layer, forming sidewall spacers above the semiconductor layer and on opposing sides of the dummy gate, forming source and drain regions on opposing sides of the sidewall spacers, and removing the dummy gate and underlying portions of the semiconductor layer between the sidewall spacers to provide a thinned channel region having a thickness less than a remainder of the semiconductor layer outside the thinned channel region. The method may further include forming a replacement gate stack over the thinned channel region and between the sidewall spacers and having a lower portion extending below a level of adjacent bottom portions of the sidewall spacers.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: August 9, 2016
    Assignees: STMICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qing Liu, Tenko Yamashita, Chun-chen Yeh, Veeraraghavan S. Basker
  • FinFET having controlled dielectric region height
    Patent number: 9412641
    Abstract: Embodiments are directed to a method of forming a dielectric region of a fin-type field effect transistor (FinFET). The method includes forming at least one fin, and forming a dielectric region adjacent a lower portion of the at least one fin, wherein the dielectric region includes a top surface. The method further includes forming a blocking layer on the top surface of the dielectric region, wherein the blocking layer is configured to prevent at least one subsequent FinFET fabrication operation from impacting the top surface of the dielectric region.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: August 9, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dechao Guo, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Method for making strained semiconductor device and related methods
    Patent number: 9406751
    Abstract: A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal treatment to form source drain extension regions, to thereby preserve the strain-inducing material in desired substitutional states.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: August 2, 2016
    Assignees: STMicroelectronics, Inc., Globalfoundries Inc, International Business Machines Corporation
    Inventors: Qing Liu, Xiuyu Cai, Ruilong Xie, Chun-chen Yeh
  • SILICON NITRIDE FILL FOR PC GAP REGIONS TO INCREASE CELL DENSITY
    Publication number: 20160218102
    Abstract: A semiconductor device is provided comprising a substrate, two or more semiconductor fins, and one or more gates. A flowable oxide layer is deposited on the semiconductor device. An area between the two or more semiconductor fins is etched such that the substrate is exposed. An insulating layer is deposited within the etched area. At least the flowable oxide layer is removed.
    Type: Application
    Filed: January 26, 2015
    Publication date: July 28, 2016
    Inventors: Dechao Guo, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • ANCHORED STRESS-GENERATING ACTIVE SEMICONDUCTOR REGIONS FOR SEMICONDUCTOR-ON-INSULATOR FINFET
    Publication number: 20160218198
    Abstract: After formation of a gate structure and a gate spacer, portions of an insulator layer underlying a semiconductor fin are etched to physically expose semiconductor surfaces of an underlying semiconductor material layer from underneath a source region and a drain region. Each of the extended source region and the extended drain region includes an anchored single crystalline semiconductor material portion that is in epitaxial alignment to the single crystalline semiconductor structure of the underlying semiconductor material layer and laterally applying a stress to the semiconductor fin. Because each anchored single crystalline semiconductor material portion is in epitaxial alignment with the underlying semiconductor material layer, the channel of the fin field effect transistor is effectively stressed along the lengthwise direction of the semiconductor fin.
    Type: Application
    Filed: April 6, 2016
    Publication date: July 28, 2016
    Inventors: Veeraraghavan S. Basker, Krishna Iyengar, Tenko Yamashita, Chun-Chen Yeh
  • IMPLANTATION FORMED METAL-INSULATOR-SEMICONDUCTOR (MIS) CONTACTS
    Publication number: 20160211342
    Abstract: A method of forming a metal-insulator-semiconductor (MIS) contact, a transistor including the MIS contact, and the MIS contact are described. The method includes etching an opening for formation of the contact, the opening extending to an upper surface of a semiconductor region. The method also includes implanting metal ions at a selected depth within the upper surface of the semiconductor region and converting the upper surface of the semiconductor region to a metal oxide insulating layer. The method further includes forming a metal layer on the insulating layer.
    Type: Application
    Filed: March 14, 2016
    Publication date: July 21, 2016
    Inventors: Chia-Yu Chen, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • IMPLANTATION FORMED METAL-INSULATOR-SEMICONDUCTOR (MIS) CONTACTS
    Publication number: 20160211340
    Abstract: A method of forming a metal-insulator-semiconductor (MIS) contact, a transistor including the MIS contact, and the MIS contact are described. The method includes etching an opening for formation of the contact, the opening extending to an upper surface of a semiconductor region. The method also includes implanting metal ions at a selected depth within the upper surface of the semiconductor region and converting the upper surface of the semiconductor region to a metal oxide insulating layer. The method further includes forming a metal layer on the insulating layer.
    Type: Application
    Filed: January 20, 2015
    Publication date: July 21, 2016
    Inventors: Chia-Yu Chen, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • IMPLANTATION FORMED METAL-INSULATOR-SEMICONDUCTOR (MIS) CONTACTS
    Publication number: 20160211343
    Abstract: A method of forming a metal-insulator-semiconductor (MIS) contact, a transistor including the MIS contact, and the MIS contact are described. The method includes etching an opening for formation of the contact, the opening extending to an upper surface of a semiconductor region. The method also includes implanting metal ions at a selected depth within the upper surface of the semiconductor region and converting the upper surface of the semiconductor region to a metal oxide insulating layer. The method further includes forming a metal layer on the insulating layer.
    Type: Application
    Filed: March 14, 2016
    Publication date: July 21, 2016
    Inventors: Chia-Yu Chen, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Fabricating shallow-trench isolation semiconductor devices to reduce or eliminate oxygen diffusion
    Patent number: 9397158
    Abstract: A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: July 19, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ming Cai, Dechao Guo, Liyang Song, Chun-chen Yeh