Patents by Inventor Chun-Chen Yeh

Chun-Chen Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PROCESS FOR INTEGRATED CIRCUIT FABRICATION INCLUDING A UNIFORM DEPTH TUNGSTEN RECESS TECHNIQUE
    Publication number: 20170012105
    Abstract: Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first length). Work function metal for a metal gate electrode is provided in the first and second openings. Tungsten is deposited to fill the first opening and conformally line the second opening, thus leaving a third opening. The thickness of the tungsten layer substantially equals the length of the first opening. The third opening is filled with an insulating material. The tungsten is then recessed in both the first and second openings using a dry etch to substantially a same depth from a top surface of the pre-metal layer to complete the metal gate electrode. Openings left following the recess operation are then filled with a dielectric material forming a cap on the gate stack which includes the metal gate electrode.
    Type: Application
    Filed: September 23, 2016
    Publication date: January 12, 2017
    Inventors: QING LIU, RUILONG XIE, CHUN-CHEN YEH
  • INCREASED CONTACT AREA FOR FINFETS
    Publication number: 20170012129
    Abstract: A method for forming fin field effect transistors includes epitaxially growing source and drain (S/D) regions on fins, the S/D regions including a diamond-shaped cross section and forming a dielectric liner over the S/D regions. A dielectric fill is etched over the S/D regions to expose a top portion of the diamond-shaped cross section. The fins are recessed into the diamond-shaped cross section. A top portion of the diamond-shaped cross section of the S/D regions is exposed. A contact liner is formed on the top portion of the diamond-shaped cross section of the S/D regions and in a recess where the fins were recessed. Contacts are formed over surfaces of the top portion and in the recess.
    Type: Application
    Filed: July 9, 2015
    Publication date: January 12, 2017
    Inventors: Veeraraghavan S. Basker, Chung-Hsun Lin, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • LARGE AREA CONTACTS FOR SMALL TRANSISTORS
    Publication number: 20170012130
    Abstract: A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.
    Type: Application
    Filed: September 23, 2016
    Publication date: January 12, 2017
    Inventors: Xiuyu CAI, Qing LIU, Ruilong XIE, Chun-Chen YEH
  • Low-K spacer for RMG finFET formation
    Patent number: 9543407
    Abstract: A method for semiconductor fabrication includes providing mask layers on opposite sides of a substrate, the substrate having one or more mandrels. Dummy spacers are formed along a periphery of the mask layers. A dummy gate structure is formed between the dummy spacers. The dummy spacers are removed to provide a recess. Low-k spacers are formed in the recess.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: January 10, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hong He, Chiahsun Tseng, Tenko Yamashita, Chun-Chen Yeh, Yunpeng Yin
  • TEST STRUCTURE MACRO FOR MONITORING DIMENSIONS OF DEEP TRENCH ISOLATION REGIONS AND LOCAL TRENCH ISOLATION REGIONS
    Publication number: 20170005014
    Abstract: Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.
    Type: Application
    Filed: July 1, 2015
    Publication date: January 5, 2017
    Inventors: Tenko Yamashita, Chun-Chen Yeh, Hui Zang
  • Localized fin width scaling using a hydrogen anneal
    Patent number: 9537015
    Abstract: Transistors including one or more semiconductor fins formed on a substrate. The one or more semiconductor fins are thinner in a channel region than in source and drain regions and have rounded corners formed by an anneal in a gaseous environment. A gate dielectric layer is on the channel region of the one or more semiconductor fins, conforming to the contours of the one or more semiconductor fins. A gate structure is on the gate dielectric layer.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: January 3, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, RENESAS ELECTRONICS CORPORATION
    Inventors: Veeraraghavan S. Basker, Shogo Mochizuki, Tenko Yamashita, Chun-Chen Yeh
  • NANOWIRE SEMICONDUCTOR DEVICE INCLUDING LATERAL-ETCH BARRIER REGION
    Publication number: 20160380083
    Abstract: A semiconductor device includes a semiconductor-on-insulator wafer having a buried oxide layer. The buried oxide layer includes therein opposing etch barrier regions and a gate region between the etch barrier regions. The semiconductor device further includes at least one nanowire having a channel portion interposed between opposing source/drain portions. The channel portion is suspended in the gate region. A gate electrode is formed in the gate region, and completely surrounds all surfaces of the suspended nanowire. The buried oxide layer comprises a first electrical insulating material, and the etch barrier regions comprising a second electrical insulating material different from the first electrical insulating material.
    Type: Application
    Filed: August 5, 2016
    Publication date: December 29, 2016
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • NANOWIRE SEMICONDUCTOR DEVICE INCLUDING LATERAL-ETCH BARRIER REGION
    Publication number: 20160380054
    Abstract: A semiconductor device includes a semiconductor-on-insulator wafer having a buried oxide layer. The buried oxide layer includes therein opposing etch barrier regions and a gate region between the etch barrier regions. The semiconductor device further includes at least one nanowire having a channel portion interposed between opposing source/drain portions. The channel portion is suspended in the gate region. A gate electrode is formed in the gate region, and completely surrounds all surfaces of the suspended nanowire. The buried oxide layer comprises a first electrical insulating material, and the etch barrier regions comprising a second electrical insulating material different from the first electrical insulating material.
    Type: Application
    Filed: August 5, 2016
    Publication date: December 29, 2016
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Replacement metal gate finFET
    Patent number: 9530651
    Abstract: A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: December 27, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hemanth Jagannathan, Sanjay C. Mehta, Junli Wang, Chun-Chen Yeh, Stefan Schmitz
  • DUAL LINER SILICIDE
    Publication number: 20160372380
    Abstract: A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.
    Type: Application
    Filed: June 16, 2015
    Publication date: December 22, 2016
    Inventors: Balasubramanian Pranatharthiharan, Ruilong Xie, Chun-Chen Yeh
  • DUAL CHANNEL FINFET WITH RELAXED PFET REGION
    Publication number: 20160372493
    Abstract: Fabricating a semiconductor device includes providing a strained semiconductor material (SSM) layer disposed on a dielectric layer, forming a first plurality of fins on the SSOI structure, at least one fin of the first plurality of fins is in a nFET region and at least one fin is in a pFET region, etching portions of the dielectric layer under portions of the SSM layer of the at least one fin in the pFET region, filling areas cleared by the etching, forming a second plurality of fins from the at least one fin in the nFET region such that each fin comprises a portion of the SSM layer disposed on the dielectric layer, and forming a third plurality of fins from the at least one fin in the pFET region such that each fin comprises a portion of the SSM layer disposed on a flowable oxide.
    Type: Application
    Filed: August 31, 2016
    Publication date: December 22, 2016
    Inventors: Xiuyu Cai, Qing Liu, Ruilong Xie, Chun-Chen Yeh
  • DUAL LINER SILICIDE
    Publication number: 20160372332
    Abstract: A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.
    Type: Application
    Filed: August 18, 2016
    Publication date: December 22, 2016
    Inventors: Balasubramanian Pranatharthiharan, Ruilong Xie, Chun-Chen Yeh
  • PUNCH THROUGH STOPPER IN BULK FINFET DEVICE
    Publication number: 20160372589
    Abstract: A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.
    Type: Application
    Filed: August 29, 2016
    Publication date: December 22, 2016
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Symmetrical extension junction formation with low-k spacer and dual epitaxial process in finFET device
    Patent number: 9525048
    Abstract: A technique relates to a dual epitaxial process a device. A first spacer is disposed on a substrate, dummy gate, and hardmask. A first area extends in a first direction from the gate and a second area extends in an opposite direction. A doped intermediate spacer is disposed on the first spacer. A first region is opened on the substrate by removing first spacer and intermediate spacer at the first region. A first epitaxial layer is disposed in the first region. The intermediate spacer is removed from first area. A second spacer is disposed on the intermediate spacer. A second region is opened on the substrate by removing the first spacer, intermediate spacer, and second spacer. A second epitaxial layer is disposed in second region. The width of the second epitaxial layer is enlarged by annealing causing dopant in the intermediate spacer layer to flow into the second epitaxial layer.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: December 20, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • SERIES RESISTANCE REDUCTION IN VERTICALLY STACKED SILICON NANOWIRE TRANSISTORS
    Publication number: 20160365411
    Abstract: Embodiments are directed to a method of fabricating a portion of a nanowire field effect transistor (FET). The method includes forming a sacrificial layer and a nanowire layer, removing a sidewall portion of the sacrificial layer and forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer. The method further includes forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region, and removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.
    Type: Application
    Filed: June 15, 2015
    Publication date: December 15, 2016
    Inventors: Chun-Chen Yeh, Xiuyu Cai, Qing Liu, Ruilong Xie
  • PUNCH THROUGH STOPPER IN BULK FINFET DEVICE
    Publication number: 20160365432
    Abstract: A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.
    Type: Application
    Filed: August 29, 2016
    Publication date: December 15, 2016
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Vertical slit transistor with optimized AC performance
    Patent number: 9515180
    Abstract: A vertical slit transistor includes raised source, drain, and channel regions in a semiconductor substrate. Two gate electrodes are positioned adjacent respective sidewalls of the semiconductor substrate. A dielectric material separates the gate electrodes from the source and drain regions.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: December 6, 2016
    Assignees: STMicroelectronics, Inc., GlobalFoundries Inc., International Business Machines Corporation
    Inventors: Qing Liu, Xiuyu Cai, Chun-chen Yeh, Ruilong Xie
  • Densely spaced fins for semiconductor fin field effect transistors
    Patent number: 9508713
    Abstract: A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: November 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
  • SALICIDE FORMATION ON REPLACEMENT METAL GATE FINFET DEVICES
    Publication number: 20160343856
    Abstract: A fin field effect transistor (finFET) device and a method of fabricating a finFET are described. The method includes forming a replacement gate stack on a substrate between inside walls of sidewall spacers, epitaxially growing a raised source drain (RSD) on the substrate adjacent to outside walls of the sidewall spacers, and forming a silicide above the RSD and along the outside walls of the sidewall spacers. The method also includes depositing and polishing a contact metal above portions of the replacement gate stack and the RSD, the contact metal contacting the silicide along the outside walls of the sidewall spacers adjacent to the portions of the replacement gate stack.
    Type: Application
    Filed: May 19, 2015
    Publication date: November 24, 2016
    Inventors: Effendi Leobandung, Soon-Cheon Seo, Tenko Yamashita, Chun-Chen Yeh
  • Multi-channel gate-all-around FET
    Patent number: 9502518
    Abstract: A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wrap-around gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: November 22, 2016
    Assignees: STMICROELECTRONICS, INC., GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qing Liu, Ruilong Xie, Chun-chen Yeh, Xiuyu Cai