Abstract: An apparatus for making wedged plate has an extruder to provide melted plastic material. A die head has a channel with an inlet and an outlet. The inlet of the die head is connected to an outlet of the extruder. The outlet of the die head has a thick side and a narrow side. A rolling device has two rollers and a space between the rollers. The space has a thick portion and a narrow portion at opposite sides. The space of the rolling device is aligned with the outlet of the die head, so that the plastic material flows into the space of the rolling device via the die head and is rolled by the rollers. A cutting device is arranged behind the rolling device to cut the rolled plastic material to get wedged plates.

Abstract: A method of forming bumps on the active surface of a silicon wafer. A first under-bump metallic layer is formed over the active surface of the wafer. A second under-bump metallic layer is formed over the first under-bump metallic layer. A portion of the second under-bump metallic layer is removed to expose the first under-bump metallic layer. A plurality of solder bumps is implanted onto the second under-bump metallic layer. The exposed first under-bump metallic layer is removed so that only the first under-bump metallic layer underneath the second under-bump metallic layer remains.

Abstract: A method for fabricating on-chip spacers for a TFT panel exposes a photoresist layer on top of the TFT panel using two exposure processes, one through the bottom of the TFT and the other through a mask over the TFT panel. The exposure process through the bottom exposes all photoresist covering windows on the TFT panel and leaves all photoresist corresponding to an opaque grid corresponding a TFT driving circuit. A second exposure process through a mask above the photoresist leaves part of the photoresist in the opaque grid unexposed. The exposed photoresist is removed leaving on-chip spacers only on the opaque grid. Therefore, the on-chip spacers can not affect the display quality and can be easily formed on a high dpi TFT panel.

Abstract: A substrate has a substrate member, which is made of Cyclic Olefins Polymer (COP) or Cyclic Olefins Copolymer (COC), and two protective layers, which are made of Polymethyl methacrylate (PMMA) or Polycarbonate (PC), provided on opposite side of the substrate member. The COP or COC substrate member has a less water absorption (<0.01%) to prevent the substrate from warping while it is irradiated at single side. The PMMA or PC protective layer has a greater hardness to protect the substrate from damage.

Abstract: A bump fabrication process for forming a bump over a wafer having a plurality of bonding pads thereon is provided. A patterned solder mask layer having a plurality of openings that exposes the respective bonding pads is formed over a wafer. The area of the opening in a the cross-sectional area through a the bottom-section as well as through a the top-section of the opening is smaller than the area of the opening in a the cross-sectional area through a the mid-section of the opening. Solder material is deposited into the opening and then a reflow process is conducted fusing the solder material together to form a spherical bump inside the opening. Finally, the solder mask layer is removed. In addition, a pre-formed bump may form on the bonding pad of the wafer prior to forming the patterned solder mask layer over the wafer having at least with an opening that exposes the pre-formed bump.

Abstract: A method of fabricating an optical substrate has the steps of: Heat a first material and a second material to their melt conditions. Stack the first material and the second material. Roll a stack of the first material and the second material and mold a surface profile on the second material by means of a roller calender with a figured texture to mold a substrate with a surface thereon. Cool the substrate and cut the substrate.

Abstract: A wafer level package structure and a method for packaging said wafer level package structure are described. The wafer level package structure at least comprises a die, a heat slug covering said die, a carrier for supporting said heat slug and said die, a plurality of wires electrically connecting said die and said carrier, and a mould compound encapsulating said die, said carrier, said heat slug and said wires. The method comprises the steps of: (a)providing a heat slug metal with a plurality of openings; (b)mounting said heat slug metal onto a wafer to dispose said openings on corresponding bonding pads of the wafer so as to expose said bonding pads; (c)sawing said combined heat slug metal and wafer into a plurality of die units; (d)attaching said die unit onto a carrier; (e)electrically connecting a plurality of wires to said die unit and said carrier; (f)encapsulating said wired die unit and said carrier.

Abstract: A bump structure on a contact pad and a fabricating process thereof. The bump comprises an under-ball-metallurgy layer, a bonding mass and a welding lump. The under-ball-metallurgy layer is formed over the contact pad and the bonding mass is formed over the under-ball-metallurgy layer by conducting a pressure bonding process. The bonding mass having a thickness between 4 to 10 ?m is made from a material such as copper. The welding lump is formed over the bonding mass such that a sidewall of the bonding mass is also enclosed.

Abstract: A substrate has a substrate member, which is made of Polymethyl methacrylate (PMMA) or Polycarbonate (PC), having a first side and a second side. On the fist side and the second side of the substrate member provided with an insulating layers respectively, wherein the insulating layers are made of Cyclic Olefins Polymer (COP). The water absorption of COP is less than the water absorption of PMMA and PC to prevent the substrate member from warping while the substrate is heated at a single side.

Abstract: A semiconductor device with a capability can prevent a burnt fuse pad from re-electrical connection, wherein the semiconductor device includes a bump pad and a fuse pad over a wafer. The fuse pad includes the burnt fuse pad having a gap for electrical isolation. The semiconductor device comprises a dielectric layer, disposed substantially above the burnt fuse pad and filling the gap, and a bump structure, disposed on the bump pad. The foregoing semiconductor device can further comprise a passivation layer, which exposes the bump pad and a portion of the burnt fuse pad. Wherein, the dielectric layer is over the passivation layer, covers the exposed portion of the burnt fuse pad and fills the gap.

Abstract: A wafer-level package structure, applicable to a flip-chip type arrangement on a carrier having a plurality of contact points is described. This wafer-level package structure comprises a chip having a protective layer and a plurality of bonding pads and a conductive layer. The conductive layer is arranged on the bonding pads of the chip as contact points. The wafer-level package structure can further include a heat sink to enhance the heat dissipation ability of the package structure.

Abstract: An under-bump-metallurgy layer is provided. The under-bump-metallurgy layer is formed over the contact pad of a chip and a welding lump is formed over the under-ball-metallurgy layer. The under-bump-metallurgy layer comprises an adhesion layer, a barrier layer and a wettable layer. The adhesion layer is directly formed over the contact pad. The barrier layer made from a material such as nickel-vanadium alloy is formed over the adhesion layer. The wettable layer made from a material such as copper is formed over the barrier layer. The wettable layer has an overall thickness that ranges from about 3 ?m to about 8 ?m.

Abstract: A method of forming a transparent conductive layer on a substrate has the steps of: forming a transparent conductive layer on a flat surface of a temporary substrate, wherein the transparent conductive layer has a first side attached onto the flat surface directly and a second side opposite to the first side; patterning the transparent conductive layer; providing an insulation layer to cover the second side of the transparent conductive layer; providing a substrate on the insulation layer, and removing the temporary substrate to expose the first side of the transparent conductive layer.

Abstract: A method of modifying the tin to lead ratio of a tin-lead bump forms a patterned solder mask over a substrate that comprises a first tin-lead bump formed thereon, the patterned solder mask having an opening that exposes the tin-lead bump. A solder material including tin and lead is filled in the opening of the solder mask over the first tin-lead bump. The solder material has a tin to lead ratio that differs from that of the first tin-lead bump. The solder material is reflowed to fuse with the first tin-lead bump, which forms a second tin-lead bump. The tin to lead ratio of the second tin-lead bump is thereby different from that of the first tin-lead bump.

Abstract: A method of forming a bump on an active surface of a wafer is disclosed. The method of the invention forms an under ball metallurgy (UBM) onto the active surface of the wafer. Then, the UBM is partially removed until a portion of the active surface of the wafer is exposed. At least one conductive stud is bonded onto the non-removed UBM by wire bonding.

Abstract: A bump structure on a contact pad and a fabricating process thereof. The bump comprises an under-ball-metallurgy layer, a bonding mass and a welding lump. The under-ball-metallurgy layer is formed over the contact pad and the bonding mass is formed over the under-ball-metallurgy layer by conducting a pressure bonding process. The bonding mass having a thickness between 4 to 10 ?m is made from a material such as copper. The welding lump is formed over the bonding mass such that a sidewall of the bonding mass is also enclosed.

Abstract: In a wire-bonding process, a chip is provided with at least a first contact pad. A chip carrier is further provided with at least a second contact pad. A plurality of stacked conductive bumps are formed on the first contact pad. A conductive wire is formed by a reverse bonding process. The conductive wire electrically connects the second contact pad of the chip carrier to the stacked conductive bumps over the first contact pad of the chip.

Abstract: A solder ball fabricating process for forming solder balls over a wafer having an active layer is provided. A patterned solder mask layer is formed over the active surface of the wafer. The patterned solder mask layer has an opening that exposes a bonding pad on the wafer. Solder material is deposited into the opening over the bonding pad. A reflow process is conducted to form a pre-solder body. The aforementioned steps are repeated so that various solder materials are fused together to form a solder ball over the bonding pad.

Abstract: A wafer bump fabrication process is provided in the present invention. A wafer with multiple bonding pads and a passivation layer, which exposes the bonding pads, is provided. The surface of each bonding pad has an under bump metallurgy layer. A patterned photoresist layer with a plurality of opening is formed which openings expose the under bump metallurgy layer. Afterwards a curing process is performed to cure the patterned photoresist layer. Following a solder paste fill-in process is performed to fill a solder paste into the openings. A reflow process is performed to form bumps from the solder paste in the openings. The patterned photoresist layer is removed.

Abstract: A method of forming bumps on the active surface of a silicon wafer. An under-ball metallic layer is formed over the active surface of the wafer. A plurality of first solder blocks is attached to the upper surface of the under-ball metallic layer. Each first solder block has an upper surface and a lower surface. The lower surface of each first solder block bonds with the under-ball metallic layer. The upper surfaces of the first solder blocks are planarized. A second solder block is attached to the upper surface of each first solder block and then a reflow operation is carried out.