Patents by Inventor Chun-Chi Yu
Chun-Chi Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12211699Abstract: A method of removing a step height on a gate structure includes providing a substrate. A gate structure is disposed on the substrate. A dielectric layer covers the gate structure and the substrate. Then, a composite material layer is formed to cover the dielectric layer. Later, part of the composite material layer is removed to form a step height disposed directly on the gate structure. Subsequently, a wet etching is performed to remove the step height. After the step height is removed, the dielectric layer is etched to form a first contact hole to expose the gate structure.Type: GrantFiled: July 4, 2022Date of Patent: January 28, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yeh-Sheng Lin, Chang-Mao Wang, Chun-Chi Yu, Chung-Yi Chiu
-
Patent number: 12188982Abstract: A test method for a delay circuit and a test circuitry are provided. The test circuitry incudes the delay circuit that essentially includes multiple serially connected logic gates, a clock pulse generator at an input end of the delay circuit for generating one or more cycles of clock signals, and a counter at an output end of the delay circuit for counting the clock signals passing through the delay circuit. The test circuitry implements a test mode by switching lines to the clock pulse generator and the counter. The test circuitry relies on a comparison result of a counting result made by the counter and a number of the cycles of the clock signals to test any failure of the delay circuit.Type: GrantFiled: July 8, 2022Date of Patent: January 7, 2025Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Kuo-Wei Chi, Chun-Chi Yu, Chih-Wei Chang
-
Publication number: 20240402915Abstract: A memory controller is arranged to access a memory device, and includes a receiving circuit. The receiving circuit is arranged to receive a data signal and a data strobe signal from the memory device, and includes a sampling circuit and a comparison circuit. The sampling circuit is arranged to sample the data signal or a delayed data signal according to a plurality of delayed versions of the data strobe signal to generate a plurality of sampling values, wherein the delayed data signal is a delayed version of the data signal. The comparison circuit is arranged to compare the plurality of sampling values to obtain a comparison result, and arranged to determine to provide the data signal or the delayed data signal to the sampling circuit according to the comparison result.Type: ApplicationFiled: May 15, 2024Publication date: December 5, 2024Applicant: Realtek Semiconductor Corp.Inventors: Shih-Chang Chen, Chih-Wei Chang, Chun-Chi Yu
-
Patent number: 12147163Abstract: A method for correcting critical dimension (CD) measurements of a lithographic tool includes steps as follows. A correction pattern having a first sub-pattern parallel to a first direction and a second sub-pattern parallel to a second direction is provided on a lithographic mask; wherein the first sub-pattern and the second sub-pattern come cross with each other. A first After-Develop-Inspection critical dimension (ADI CD) of a developed pattern formed on a photo-sensitive layer and transferred from the correction pattern is measured using the lithographic tool along a first scanning direction. A second ADI CD of the developed pattern is measured using the lithographic tool along a second scanning direction. The first ADI CD is subtracted from the second ADI CD to obtain a measurement bias value. Exposure conditions and/or measuring parameters of the lithographic tool are adjusted according to the measurement bias value.Type: GrantFiled: November 17, 2021Date of Patent: November 19, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsin-Yu Hsieh, Kuan-Ying LAi, Chang-Mao Wang, Chien-Hao Chen, Chun-Chi Yu
-
Patent number: 12106962Abstract: The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.Type: GrantFiled: June 7, 2021Date of Patent: October 1, 2024Assignee: United Microelectronics Corp.Inventors: Yi Jing Wang, Chia-Chang Hsu, Chien-Hao Chen, Chang-Mao Wang, Chun-Chi Yu
-
Publication number: 20240310869Abstract: The present disclosure discloses a memory access interface device. A signal training circuit is configured for performing following steps. A transmitting circuit transmits a training data signal and a training data strobe signal as an output data signal and an output data strobe signal to a memory device according to timing reference signals. A read data signal from the memory device is received. The training data signal and the read data signal are compared to generate a comparison result indicating whether the read data signal matches the training data signal. The comparison result is stored. The clock generation circuit is controlled to modify a phase of one of the timing reference signals, further modifying the timing of one of the training data signal and the training data strobe signal, to be one of under-test phases to execute a new loop of a training process.Type: ApplicationFiled: March 17, 2023Publication date: September 19, 2024Inventors: FU-CHIN TSAI, CHUN-CHI YU, GER-CHIH CHOU, CHIH-WEI CHANG
-
Patent number: 12088359Abstract: An eye diagram measuring method includes: sampling a compensated input signal according to a reference voltage and a reference clock to obtain a first sampling result; and sampling a to-be-compensated input signal according to a scan voltage and a scan clock to obtain a second sampling result, including: (b1) storing a minimum phase and a voltage level which render the first sampling result identical to the second sampling result; (b2) increasing the voltage level and repeating operation (b1); (b3) decreasing the voltage level and repeating operation (b1); (b4) storing a maximum phase and the voltage level which render the first sampling result identical to the second sampling result; (b5) increasing the voltage level and repeating operation (b4); and (b6) decreasing the voltage level and repeating operation (b4). Voltage levels, maximum phases and minimum phases that are stored are for adjusting the reference voltage and the reference clock.Type: GrantFiled: October 5, 2022Date of Patent: September 10, 2024Assignee: Realtek Semiconductor CorporationInventors: Shih-Chang Chen, Chih-Wei Chang, Chun-Chi Yu
-
Publication number: 20240231416Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference signals. A transmitter transmits an output command and address signal to a memory device according to the reference signals. A signal training circuit executes a training process in a training mode that includes steps outlined below. A training signal is generated such that the training signal is transmitted as the output command and address signal. The training signal and the data signal generated by the memory device are compared to generate a comparison result indicating whether the data signal matches the training signal. The comparison result is stored. The clock generation circuit is controlled to modify a phase of at least one of the reference signals to be one of a plurality of under-test phases to execute a new loop of the training process until all the under-test phases are trained.Type: ApplicationFiled: October 25, 2022Publication date: July 11, 2024Inventors: FU-CHIN TSAI, GER-CHIH CHOU, CHUN-CHI YU, CHIH-WEI CHANG, MIN-HAN TSAI
-
Publication number: 20240233837Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference clock signals. Each of access signal transmission circuits each includes a duty cycle adjusting circuit, a duty cycle detection circuit, a frequency division circuit and an asynchronous first-in-first-out circuit. The duty cycle adjusting circuit performs duty cycle adjustment on one of the reference clock signals according to a duty cycle detection signal to generate an output clock signal having a duty cycle. The duty cycle detection circuit detects a variation of the duty cycle to generate the duty cycle detection signal. The frequency division circuit divides a frequency of the output clock signal to generate a read clock signal. The asynchronous first-in-first-out circuit receives an access signal from a memory access controller and outputs an output access signal according to the read clock signal to access the memory device accordingly.Type: ApplicationFiled: October 25, 2022Publication date: July 11, 2024Inventors: FU-CHIN TSAI, GER-CHIH CHOU, CHUN-CHI YU, CHIH-WEI CHANG
-
Patent number: 12009056Abstract: The present invention discloses a data transmission apparatus having clock gating mechanism. Each of data transmission circuits has a flip-flop depth of N and receives a write clock signal and one of read clock signals to receive and output one of data signals. A write clock gating circuit receives a write clock gating enabling signal to transmit the write clock signal to the data transmission circuits. Each of read clock gating circuits receives one of read clock gating enabling signals to transmit one of the read clock signals. The gating signal transmission circuit has a flip-flop depth of N+M and receives the write and the read clock signals to receive the write clock gating enabling signal and output the read clock gating enabling signals. A largest timing difference among the read clock signals is P clock cycles and M is at least ?P?.Type: GrantFiled: July 11, 2022Date of Patent: June 11, 2024Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Fu-Chin Tsai, Ger-Chih Chou, Chun-Chi Yu, Chih-Wei Chang, Shih-Han Lin
-
Patent number: 11978497Abstract: Disclosed is a DDR SDRAM signal calibration device capable of adapting to the variation of voltage and/or temperature. The device includes: an enablement signal setting circuit configured to generate data strobe (DQS) enablement setting; a signal gating circuit configured to generate a DQS enablement setting signal and a DQS enablement signal according to the DQS enablement setting and then output a gated DQS signal according to the DQS enablement signal and a DQS signal; and a calibration circuit configured to generate a first delay signal according to the DQS enablement setting signal and generate a second delay signal according to the first delay signal, the calibration circuit further configured to generate a calibration signal according to the first and second delay signals and the DQS signal. The enablement signal setting circuit maintains or adjusts the DQS enablement setting according to the calibration signal.Type: GrantFiled: November 17, 2021Date of Patent: May 7, 2024Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Kuo-Wei Chi, Chun-Chi Yu, Chih-Wei Chang, Ger-Chih Chou
-
Publication number: 20240135999Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference clock signals. Each of access signal transmission circuits each includes a duty cycle adjusting circuit, a duty cycle detection circuit, a frequency division circuit and an asynchronous first-in-first-out circuit. The duty cycle adjusting circuit performs duty cycle adjustment on one of the reference clock signals according to a duty cycle detection signal to generate an output clock signal having a duty cycle. The duty cycle detection circuit detects a variation of the duty cycle to generate the duty cycle detection signal. The frequency division circuit divides a frequency of the output clock signal to generate a read clock signal. The asynchronous first-in-first-out circuit receives an access signal from a memory access controller and outputs an output access signal according to the read clock signal to access the memory device accordingly.Type: ApplicationFiled: October 24, 2022Publication date: April 25, 2024Inventors: FU-CHIN TSAI, GER-CHIH CHOU, CHUN-CHI YU, CHIH-WEI CHANG
-
Publication number: 20240134410Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference signals. A transmitter transmits an output command and address signal to a memory device according to the reference signals. A signal training circuit executes a training process in a training mode that includes steps outlined below. A training signal is generated such that the training signal is transmitted as the output command and address signal. The training signal and the data signal generated by the memory device are compared to generate a comparison result indicating whether the data signal matches the training signal. The comparison result is stored. The clock generation circuit is controlled to modify a phase of at least one of the reference signals to be one of a plurality of under-test phases to execute a new loop of the training process until all the under-test phases are trained.Type: ApplicationFiled: October 24, 2022Publication date: April 25, 2024Inventors: FU-CHIN TSAI, GER-CHIH CHOU, CHUN-CHI YU, CHIH-WEI CHANG, MIN-HAN TSAI
-
Publication number: 20240013824Abstract: The present invention discloses a data transmission apparatus having clock gating mechanism. Each of data transmission circuits has a flip-flop depth of N and receives a write clock signal and one of read clock signals to receive and output one of data signals. A write clock gating circuit receives a write clock gating enabling signal to transmit the write clock signal to the data transmission circuits. Each of read clock gating circuits receives one of read clock gating enabling signals to transmit one of the read clock signals. The gating signal transmission circuit has a flip-flop depth of N+M and receives the write and the read clock signals to receive the write clock gating enabling signal and output the read clock gating enabling signals. A largest timing difference among the read clock signals is P clock cycles and M is at least [P].Type: ApplicationFiled: July 11, 2022Publication date: January 11, 2024Inventors: FU-CHIN TSAI, GER-CHIH CHOU, CHUN-CHI YU, CHIH-WEI CHANG, SHIH-HAN LIN
-
Publication number: 20240007208Abstract: An eye diagram measuring method includes: sampling a compensated input signal according to a reference voltage and a reference clock to obtain a first sampling result; and sampling a to-be-compensated input signal according to a scan voltage and a scan clock to obtain a second sampling result, including: (b1) storing a minimum phase and a voltage level which render the first sampling result identical to the second sampling result; (b2) increasing the voltage level and repeating operation (b1); (b3) decreasing the voltage level and repeating operation (b1); (b4) storing a maximum phase and the voltage level which render the first sampling result identical to the second sampling result; (b5) increasing the voltage level and repeating operation (b4); and (b6) decreasing the voltage level and repeating operation (b4). Voltage levels, maximum phases and minimum phases that are stored are for adjusting the reference voltage and the reference clock.Type: ApplicationFiled: October 5, 2022Publication date: January 4, 2024Inventors: Shih-Chang CHEN, Chih-Wei CHANG, Chun-Chi YU
-
Publication number: 20230402288Abstract: A method of removing a step height on a gate structure includes providing a substrate. A gate structure is disposed on the substrate. A dielectric layer covers the gate structure and the substrate. Then, a composite material layer is formed to cover the dielectric layer. Later, part of the composite material layer is removed to form a step height disposed directly on the gate structure. Subsequently, a wet etching is performed to remove the step height. After the step height is removed, the dielectric layer is etched to form a first contact hole to expose the gate structure.Type: ApplicationFiled: July 4, 2022Publication date: December 14, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yeh-Sheng Lin, Chang-Mao Wang, Chun-Chi Yu, Chung-Yi Chiu
-
Patent number: 11823770Abstract: The present disclosure discloses a memory access interface device. A data processing circuit receives a data signal including 2M pieces of data from a memory device. A sampling clock generation circuit receives a data strobe signal from the memory device to generate a valid data strobe signal having P valid strobe pulses and further generate a sampling clock signal accordingly, in which P is larger than M. A sampling circuit samples the data signal according to the sampling clock signal to generate sampling results. A control circuit determines valid sampling results according to a time difference between the valid data strobe signal and the data signal and outputs valid data generated according to the valid sampling results as a read data signal to a memory access controller.Type: GrantFiled: May 3, 2022Date of Patent: November 21, 2023Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Ger-Chih Chou, Chih-Wei Chang, Li-Jun Gu, Chun-Chi Yu, Fu-Chin Tsai
-
Patent number: 11816352Abstract: A processor circuit sends a read request. A clock signal of the processor circuit corresponds to a first counting value. A memory circuit stores data and sends a data strobe signal in response to the read request. The data strobe signal corresponds to a second counting value. The processor circuit includes a selector circuit and a feedback circuit. The selector circuit selects and outputs a flag signal from a plurality of flag control signals according to the second counting value. The feedback circuit generates an enable signal according to a set signal associated with the first counting value, the flag signal associated with the second counting value, and a data strobe gate signal, and generates the data strobe gate signal according to the enable signal and the data strobe signal. The processor circuit reads the data according to the data strobe gate signal.Type: GrantFiled: October 22, 2021Date of Patent: November 14, 2023Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chun-Chi Yu, Chih-Wei Chang, Gerchih Chou
-
Publication number: 20230360683Abstract: The present disclosure discloses a memory access interface device. A data processing circuit receives a data signal including 2M pieces of data from a memory device. A sampling clock generation circuit receives a data strobe signal from the memory device to generate a valid data strobe signal having P valid strobe pulses and further generate a sampling clock signal accordingly, in which P is larger than M. A sampling circuit samples the data signal according to the sampling clock signal to generate sampling results. A control circuit determines valid sampling results according to a time difference between the valid data strobe signal and the data signal and outputs valid data generated according to the valid sampling results as a read data signal to a memory access controller.Type: ApplicationFiled: May 3, 2022Publication date: November 9, 2023Inventors: GER-CHIH CHOU, CHIH-WEI CHANG, LI-JUN GU, CHUN-CHI YU, FU-CHIN TSAI
-
Publication number: 20230307038Abstract: A method for calibrating a data reception window includes: (A) setting a level of a reference voltage by different predetermined values and repeatedly sampling a data signal to obtain multiple first valid data reception windows; (B) establishing a first eye diagram based on the first valid data reception windows; (C) resetting the level of the reference voltage by the predetermined values combined with a first offset and repeatedly sampling the data signal according to the reference voltage to obtain multiple second valid data reception windows and (D) selectively updating the first eye diagram according to the second valid data reception windows. When width of a second valid data reception window is greater than width of a first valid data reception window corresponding to the same predetermined value, the first valid data reception window in the first eye diagram is replaced by the second valid data reception window.Type: ApplicationFiled: March 9, 2023Publication date: September 28, 2023Applicant: Realtek Semiconductor Corp.Inventors: Shih-Chang Chen, Chih-Wei Chang, Chun-Chi Yu