Patents by Inventor Chun-Chi Yu
Chun-Chi Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150293461Abstract: An overlap mark set is provided to have at least a first and a second overlap marks both of which are located at the same pattern layer. The first overlap mark includes at least two sets of X-directional linear patterns, having a preset offset a1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset a1 therebetween. The second overlap mark includes at least two sets of X-directional linear patterns, having a preset offset b1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset b1 therebetween. The preset offsets a1 and b1 are not equal.Type: ApplicationFiled: May 15, 2014Publication date: October 15, 2015Applicant: United Microelectronics Corp.Inventors: En-Chiuan Liou, Chia-Chang Hsu, Yi-Ting Chen, Teng-Chin Kuo, Chun-Chi Yu
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Publication number: 20150276382Abstract: A measurement mark structure includes a mark pattern and a pair of assistant bars positioned at two opposite sides of the mark pattern. The mark pattern includes a plurality of segments. The segments of the mark pattern are arranged along a first direction and the pair of the assistant bars are expend along the first direction.Type: ApplicationFiled: March 27, 2014Publication date: October 1, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: En-Chiuan Liou, Kuei-Chun Hung, Chun-Chi Yu
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Patent number: 9147601Abstract: The present invention provides a method of forming via holes. First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a blocking layer are formed on the substrate. A patterned layer is formed on the blocking layer such that a sidewall of the blocking layer is completely covered by the patterned layer. The patterned layer includes a plurality of holes arranged in a regular array wherein the area of the hole array is greater than those of the first areas. The blocking layer in the first areas is removed by using the patterned layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first area.Type: GrantFiled: November 14, 2014Date of Patent: September 29, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Han Wu, Chun-Chi Yu
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Patent number: 9136140Abstract: A patterning method is provided. First, a material layer is formed over a substrate. Thereafter, a plurality of directed self-assembly (DSA) patterns are formed on the material layer. Afterwards, a patterned photoresist layer is formed by using a single lithography process. The patterned photoresist layer covers a first portion of the DSA patterns and exposes a second portion of the DSA patterns. Further, the material layer is patterned by an etching process, using the patterned photoresist layer and the second portion of the DSA patterns as a mask.Type: GrantFiled: September 12, 2013Date of Patent: September 15, 2015Assignee: United Microelectronics Corp.Inventors: Wen-Liang Huang, Chia-Hung Lin, Chun-Chi Yu
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Patent number: 9135980Abstract: This invention discloses a memory control circuit and method of controlling a data reading process of a memory module. In the data reading process, the memory module transmits a data signal and a data strobe signal used to recover the data signal. The data strobe signal includes a preamble part. The method includes steps of: controlling an impedance matching circuit of the memory module so that the data strobe signal is kept at a fixed level before the preamble part; generating a clock; generating an enabling signal according to the clock; sampling the data strobe signal according to the enabling signal to generate a sampled result; adjusting an enabling time of the enabling signal according to the sampled result; and starting a data recovering process for the data signal according to the enabling signal.Type: GrantFiled: July 9, 2014Date of Patent: September 15, 2015Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Chun-Chi Yu, Chih-Wei Chang, Shen-Kuo Huang
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Patent number: 9007571Abstract: A measurement method of an overlay mark is provided. An overlay mark on a wafer is measured with a plurality of different wavelength regions of an optical measurement tool, so as to obtain a plurality of overlay values corresponding to the wavelength regions. The overlay mark on the wafer is measured with an electrical measurement tool to obtain a reference overlay value. The wavelength region that corresponds to the overlay value closest to the reference overlay value is determined as a correct wavelength region for the overlay mark.Type: GrantFiled: August 20, 2013Date of Patent: April 14, 2015Assignee: United Microelectronics Corp.Inventors: Wei-Jhe Tzai, Kuei-Chun Hung, Chun-Chi Yu, Chien-Hao Chen, Chia-Ching Lin
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Publication number: 20150072532Abstract: A patterning method is provided. First, a material layer is formed over a substrate. Thereafter, a plurality of directed self-assembly (DSA) patterns are formed on the material layer. Afterwards, a patterned photoresist layer is formed by using a single lithography process. The patterned photoresist layer covers a first portion of the DSA patterns and exposes a second portion of the DSA patterns. Further, the material layer is patterned by an etching process, using the patterned photoresist layer and the second portion of the DSA patterns as a mask.Type: ApplicationFiled: September 12, 2013Publication date: March 12, 2015Applicant: United Microelectronics Corp.Inventors: Wen-Liang Huang, Chia-Hung Lin, Chun-Chi Yu
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Publication number: 20150072529Abstract: The present invention provides a method of forming via holes. First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a blocking layer are formed on the substrate. A patterned layer is formed on the blocking layer such that a sidewall of the blocking layer is completely covered by the patterned layer. The patterned layer includes a plurality of holes arranged in a regular array wherein the area of the hole array is greater than those of the first areas. The blocking layer in the first areas is removed by using the patterned layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first area.Type: ApplicationFiled: November 14, 2014Publication date: March 12, 2015Inventors: Cheng-Han Wu, Chun-Chi Yu
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Publication number: 20150055125Abstract: A measurement method of an overlay mark is provided. An overlay mark on a wafer is measured with a plurality of different wavelength regions of an optical measurement tool, so as to obtain a plurality of overlay values corresponding to the wavelength regions. The overlay mark on the wafer is measured with an electrical measurement tool to obtain a reference overlay value. The wavelength region that corresponds to the overlay value closest to the reference overlay value is determined as a correct wavelength region for the overlay mark.Type: ApplicationFiled: August 20, 2013Publication date: February 26, 2015Applicant: United Microelectronics Corp.Inventors: Wei-Jhe Tzai, Kuei-Chun Hung, Chun-Chi Yu, Chien-Hao Chen, Chia-Ching Lin
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Publication number: 20150049562Abstract: This invention discloses a memory control circuit and method of controlling a data reading process of a memory module. In the data reading process, the memory module transmits a data signal and a data strobe signal used to recover the data signal. The data strobe signal includes a preamble part. The method includes steps of: controlling an impedance matching circuit of the memory module so that the data strobe signal is kept at a fixed level before the preamble part; generating a clock; generating an enabling signal according to the clock; sampling the data strobe signal according to the enabling signal to generate a sampled result; adjusting an enabling time of the enabling signal according to the sampled result; and starting a data recovering process for the data signal according to the enabling signal.Type: ApplicationFiled: July 9, 2014Publication date: February 19, 2015Inventors: Chun-Chi Yu, Chih-Wei Chang, Shen-Kuo Huang
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Patent number: 8916051Abstract: The present invention provides a method of forming via holes. First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a blocking layer are formed on the substrate. A patterned photoresist layer is formed on the blocking layer. The patterned photoresist layer includes a plurality of holes arranged in a regular array wherein the area of the hole array is greater than those of the first areas. The blocking layer in the first areas is removed by using the patterned photoresist layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first area.Type: GrantFiled: December 23, 2010Date of Patent: December 23, 2014Assignee: United Microelectronics Corp.Inventors: Cheng-Han Wu, Chun-Chi Yu
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Patent number: 8729716Abstract: An alignment accuracy (AA) mark is described, including N (N?3) pattern sets defined by N exposure steps respectively. The N exposure steps are performed also to a device area disposed on a wafer together with the AA mark. The i-th (i=1, 2 . . . N?1) pattern set surrounds the (i+1)-th pattern set. Each pattern set includes a 1st set of x-directional linear patterns, a 2nd set of x-directional linear patterns arranged opposite to the 1st set of x-directional linear patterns in the y-direction, a 1st set of y-directional linear patterns, and a 2nd set of y-directional linear patterns arranged opposite to the 1st set of y-directional linear patterns in the x-direction, wherein each set of x- or y-directional linear patterns include at least three separate parallel linear patterns.Type: GrantFiled: October 31, 2011Date of Patent: May 20, 2014Assignee: United Microelectronics Corp.Inventors: Kai-Lin Chuang, Wen-Liang Huang, Chia-Hung Lin, Chun-Chi Yu
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Publication number: 20140120476Abstract: A method of forming a photoresist pattern, in which, a substrate is coated with a photoresist layer, an exposure process is performed on the photoresist layer to expose the photoresist layer, the photoresist layer is rinsed with a surfactant after the exposure process is performed, and the photoresist layer is post-exposure baked after the photoresist layer is rinsed with the surfactant.Type: ApplicationFiled: October 26, 2012Publication date: May 1, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Tuan-Yen Yu, Yuan-Chi Pai, Chun-Chi Yu
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Patent number: 8564143Abstract: An overlay mark is described, including N (N?2) groups of first x-directional linear patterns each defined from a different one of N pre-layers, N groups of second x-directional linear patterns of a current layer, N groups of first y-directional linear patterns each defined from a different one of the N pre-layers, and N groups of second y-directional linear patterns of the current layer. Each group of second x-directional linear patterns is disposed together with one group of first x-directional linear patterns, wherein the second linear patterns and the x-directional linear patterns are arranged alternately. Each group of second y-directional linear patterns is disposed together with one group of first y-directional linear patterns, wherein the second linear patterns and the first linear patterns are arranged alternately.Type: GrantFiled: February 6, 2012Date of Patent: October 22, 2013Assignee: United Microelectronics Corp.Inventors: Yi-Ting Chen, Chien-Hao Chen, Yuan-Chi Pai, Chun-Chi Yu
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Publication number: 20130200535Abstract: An overlay mark is described, including N (N?2) groups of first x-directional linear patterns each defined from a different one of N pre-layers, N groups of second x-directional linear patterns of a current layer, N groups of first y-directional linear patterns each defined from a different one of the N pre-layers, and N groups of second y-directional linear patterns of the current layer. Each group of second x-directional linear patterns is disposed together with one group of first x-directional linear patterns, wherein the second linear patterns and the x-directional linear patterns are arranged alternately. Each group of second y-directional linear patterns is disposed together with one group of first y-directional linear patterns, wherein the second linear patterns and the first linear patterns are arranged alternately.Type: ApplicationFiled: February 6, 2012Publication date: August 8, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-Ting Chen, Chien-Hao Chen, Yuan-Chi Pai, Chun-Chi Yu
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Patent number: 8476004Abstract: A method for forming photoresist patterns includes providing a substrate, forming a bi-layered photoresist on the substrate, and performing a photolithography process to pattern the bi-layered photoresist. The bi-layered photoresist includes a first photoresist layer and a second photoresist layer positioned between the first photoresist layer and the substrate. The first photoresist layer has a first refraction index and the second photoresist layer has a second refraction index, and the second refraction index is larger than the first refraction index.Type: GrantFiled: June 27, 2011Date of Patent: July 2, 2013Assignee: United Microelectronics Corp.Inventors: Yong-Fa Huang, Cheng-Han Wu, Yuan-Chi Pai, Chun-Chi Yu, Hung-Yi Wu
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Publication number: 20130106000Abstract: An alignment accuracy (AA) mark is described, including N (N?3) pattern sets defined by N exposure steps respectively. The N exposure steps are performed also to a device area disposed on a wafer together with the AA mark. The i-th (i=1, 2 . . . N?1) pattern set surrounds the (i+1)-th pattern set. Each pattern set includes a 1st set of x-directional linear patterns, a 2nd set of x-directional linear patterns arranged opposite to the 1st set of x-directional linear patterns in the y-direction, a 1st set of y-directional linear patterns, and a 2nd set of y-directional linear patterns arranged opposite to the 1st set of y-directional linear patterns in the x-direction, wherein each set of x- or y-directional linear patterns include at least three separate parallel linear patterns.Type: ApplicationFiled: October 31, 2011Publication date: May 2, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kai-Lin Chuang, Wen-Liang Huang, Chia-Hung Lin, Chun-Chi Yu
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Publication number: 20120329280Abstract: A method for forming photoresist patterns includes providing a substrate, forming a bi-layered photoresist on the substrate, and performing a photolithography process to pattern the bi-layered photoresist. The bi-layered photoresist includes a first photoresist layer and a second photoresist layer positioned between the first photoresist layer and the substrate. The first photoresist layer has a first refraction index and the second photoresist layer has a second refraction index, and the second refraction index is larger than the first refraction index.Type: ApplicationFiled: June 27, 2011Publication date: December 27, 2012Inventors: Yong-Fa Huang, Cheng-Han Wu, Yuan-Chi Pai, Chun-Chi Yu, Hung-Yi Wu
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Publication number: 20120164835Abstract: The present invention provides a method of forming via holes. First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a blocking layer are formed on the substrate. A patterned photoresist layer is formed on the blocking layer. The patterned photoresist layer includes a plurality of holes arranged in a regular array wherein the area of the hole array is greater than those of the first areas. The blocking layer in the first areas is removed by using the patterned photoresist layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first area.Type: ApplicationFiled: December 23, 2010Publication date: June 28, 2012Inventors: Cheng-Han Wu, Chun-Chi Yu
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Patent number: 7633601Abstract: To avoid the yield of wafers that undergo immersion lithography influencing by delay of post exposure baking (PEB), an operation system adjusts a speed of inputting the wafers to undergo immersion lithography according to a status of wafers that have finished exposure and are waiting for baking. Therefore, the wafers that have finished exposure are transmitted to be baked efficiently and on time.Type: GrantFiled: March 14, 2006Date of Patent: December 15, 2009Assignee: United Microelectronics Corp.Inventors: Yong-Fa Huang, Benjamin Szu-Min Lin, Chun-Chi Yu, Huan-Ting Tseng, Bo-Jou Lu