Abstract: An underwater ultrasonic device includes at least one first ultrasonic transducer and at least one second ultrasonic transducer. The first ultrasonic transducer is configured to transmit a plurality of ultrasonic signals and the second ultrasonic transducer is configured to receive a plurality of reflected signals of the ultrasonic signals. The first ultrasonic transducer and the second ultrasonic transducer are disposed with respect to each other. One of the first ultrasonic transducer and the second ultrasonic transducer is curvilinear and another one of the first ultrasonic transducer and the second ultrasonic transducer is curvilinear or straight linear.

Abstract: A data processing method is proposed, including: sensing, via at least one sensing portion, target information of a target device; receiving and processing, via an electronic device, the target information of the sensing portion to form feature information; processing, via the electronic device, the feature information into a label matrix, and establishing, via an artificial intelligence training method, a target model based on the label matrix; and after the electronic device captures real-time information of the target device, predicting, via the target model, a life limit of the target device, wherein a content of the target information is corresponding to a content of the real-time information. Thus, a good target model is constituted and is advantageous in training artificial intelligence by processing the feature information into the label matrix.

Abstract: Provided is an electronic device and an electric energy conversion method. The electronic device includes at least one moving component, a transducer system, a charging and discharging system, and a power supply system. The transducer system has at least one piezoelectric membrane and a storage unit. The at least one piezoelectric membrane is disposed on the at least one moving component, and the storage unit is electrically coupled to the at least one piezoelectric membrane. The charging and discharging system is electrically coupled to the at least one moving component and the transducer system. The power supply system is electrically coupled to the at least one moving component, the transducer system, and the charging and discharging system to provide main energy. The at least one moving component starts to operate, the at least one moving component leads the at least one piezoelectric membrane to deform elastically to generate assisting charges.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure and a gate spacer formed on a sidewall surface of the gate structure. The semiconductor structure also includes a first source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate spacer, and a second S/D epitaxial layer formed over the first S/D epitaxial layer. A top surface of the second S/D layer is higher than a top surface of the first S/D epitaxial layer.

Abstract: A heat dissipation module including a chamber, a first cooling member, and a barrier part is provided. The chamber has an accommodating space, at least one inlet, and at least one outlet. The at least one inlet is disposed in a first side wall of the chamber and communicates with the accommodating space. The at least one outlet is disposed in a second side wall of the chamber away from the at least one inlet and communicates with the accommodating space. The first cooling member is disposed in the accommodating space. The first cooling member has a guiding surface which extends obliquely upward. The barrier part is disposed outside the guiding surface of the first cooling member and has at least one through hole.

Abstract: A method of producing a fouling-proof structure, comprising steps of a) coating an alcohol-resistant combination on a substrate and then drying the alcohol-resistant combination at 80-160° C. to form an alcohol-resistant layer; and b) coating a water-based fouling-proof combination on the alcohol-resistant layer and then drying the water-based fouling-proof combination above 140° C. to form a water-based fouling-proof layer, wherein the alcohol-resistant layer is formed by curing an alcohol-resistant combination, and the alcohol-resistant combination comprises polyurethane resin, wherein the water-based fouling-proof layer is formed by curing a water-based fouling-proof combination, and the water-based fouling-proof combination comprises polyurethane resin, water, polymerized siloxanes, water-based PTFE and silicone oil.

Abstract: A fouling-proof structure is applicable to synthetic leather or fabric and it includes an alcohol-resistant layer; and a water-based fouling-proof layer disposed on the alcohol-resistant layer, wherein the alcohol-resistant layer is formed by curing an alcohol-resistant combination, and the alcohol-resistant combination comprises polyurethane resin, wherein the water-based fouling-proof layer is formed by curing a water-based fouling-proof combination, and the water-based fouling-proof combination comprises polyurethane resin, water, polymerized siloxanes, water-based PTFE and silicone oil.

Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.

Abstract: Provided is a capacitor structure including a substrate, a cup-shaped lower electrode, a top supporting layer, a capacitor dielectric layer, and an upper electrode. The cup-shaped lower electrode is located on the substrate. The top supporting layer surrounds the upper portion of the cup-shaped lower electrode. The top supporting layer includes a high-k material. Surfaces of the cup-shaped lower electrode and the top supporting layer are covered by the capacitor dielectric layer. A surface of the capacitor dielectric layer is covered by the upper electrode.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate stack to partially cover a semiconductor structure. The method also includes forming a first semiconductor material over the semiconductor structure. The method further includes forming a second semiconductor material over the first semiconductor material. In addition, the method includes forming a third semiconductor material over the second semiconductor material. The first semiconductor material and the third semiconductor material together surround the second semiconductor material. The second semiconductor material has a greater dopant concentration than that of the first semiconductor material or that of the third semiconductor material.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a fin structure extending above a substrate. The fin structure includes a channel region, a portion of the channel region is made of silicon germanium (SiGe), and the silicon germanium (SiGe) has a gradient germanium (Ge) concentration. The FinFET device structure includes a gate structure formed on the channel region of the fin structure.

Abstract: The present disclosure describes an exemplary fabrication method of a p-type fully strained channel that can suppress the formation of {111} facets during a silicon germanium epitaxial growth. The exemplary method includes the formation of silicon epitaxial layer on a top, carbon-doped region of an n-type region. A recess is formed in the silicon epitaxial layer via etching, where the recess exposes the top, carbon-doped region of the n-type region. A silicon seed layer is grown in the recess, and a silicon germanium layer is subsequently epitaxially grown on the silicon seed layer to fill the recess. The silicon seed layer can suppress the formation of growth defects such as, for example, {111} facets, during the silicon germanium epitaxial layer growth.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

Abstract: A FinFET device and method of forming the same are disclosed. The method includes forming a gate dielectric layer and depositing a metal oxide layer over the gate dielectric layer. The method also includes annealing the gate dielectric layer and the metal oxide layer, causing ions to diffuse from the metal oxide layer to the gate dielectric layer to form a doped gate dielectric layer. The method also includes forming a work function layer over the doped gate dielectric layer, and forming a gate electrode over the work function layer.

Abstract: A communication device includes a display device, a first antenna element, a second antenna element, a third antenna element, and a fourth antenna element. The display device is surrounded by the first antenna element, the second antenna element, the third antenna element, and the fourth antenna element. Any adjacent two of the first antenna element, the second antenna element, the third antenna element, and the fourth antenna element have different polarization directions.

Abstract: A centrifugal heat dissipation fan including a housing and an impeller is provided. The housing has at least one inlet and at least one outlet. The impeller is disposed in the housing and rotates about an axis. The inlet is located in an axial direction of the axis and corresponds to the impeller. The outlet is located in a radial direction relative to the axis. The inlet is divided into a compression section and a release section in the rotation direction of the impeller, and the compression section has a uniform first radial dimension relative to the axis. The release section has an extended second radial dimension relative to the axis, and the second radial dimension is greater than the first radial dimension.

Abstract: An underwater ultrasonic device includes at least one first ultrasonic transducer and at least one second ultrasonic transducer. The first ultrasonic transducer is configured to transmit a plurality of ultrasonic signals and the second ultrasonic transducer is configured to receive a plurality of reflected signals of the ultrasonic signals. The first ultrasonic transducer and the second ultrasonic transducer are disposed with respect to each other. One of the first ultrasonic transducer and the second ultrasonic transducer is curvilinear and another one of the first ultrasonic transducer and the second ultrasonic transducer is curvilinear or straight linear.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

Abstract: A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.