Abstract: An antenna structure and a head mounted display device are provided. The antenna structure includes a first structure body, a second structure body and a feeding element. The first structure body receives a reference ground voltage. The second structure body is coupled to the first structure body. The second structure body includes a conductive part, a shaft sleeves part and a shaft body, the shaft body passes through the shaft sleeves part, the shaft body is electronically coupled to the conductive part, and the conductive part is coupled to a feed point. The feeding element is coupled to the feed point and the first structure body, and is used for transmitting and receiving a radio frequency signal.

Abstract: A wideband antenna system includes a first metal radiation portion, having a coupling distance with a second metal radiation portion; a first feeding contact and a second feeding contact, electrically connected to the first metal radiation portion and the second metal radiation portion respectively, and close to the coupling distance; a first ground contact, electrically connected to the second metal radiation portion; a second ground contact, electrically connected to the first metal radiation portion; an impedance tuner, electrically connected to the first feeding contact, the second feeding contact, the first ground contact, the second ground contact, and a radio frequency signal source, to switch the first metal radiation portion and the second metal radiation portion; an aperture contact, electrically connected to the first metal radiation portion; and an aperture tuner, electrically connected to the aperture contact.

Abstract: Provided is a ferroelectric memory device having a multi-layer stack disposed over a substrate and including a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A plurality of ferroelectric portions are discretely disposed between the channel layer and the plurality of conductive layers. The plurality of ferroelectric portions are vertically separated from one another by one or more non-zero distances.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.

Abstract: In a method of manufacturing a photo mask, a resist layer is formed over a mask blank, which includes a mask substrate, a phase shift layer disposed on the mask substrate and a light blocking layer disposed on the phase shift layer. A resist pattern is formed by using a lithographic operation. The light blocking layer is patterned by using the resist pattern as an etching mask. The phase shift layer is patterned by using the patterned light blocking layer as an etching mask. A border region of the mask substrate is covered with an etching hard cover, while a pattern region of the mask substrate is opened. The patterned light blocking layer in the pattern region is patterned through the opening of the etching hard cover. A photo-etching operation is performed on the pattern region to remove residues of the light blocking layer.

Abstract: Provided are a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes: a gate electrode; a ferroelectric layer, disposed on the gate electrode; a channel layer, disposed on the ferroelectric layer; a pair of source/drain (S/D) electrodes, disposed on the channel layer; a first insertion layer, disposed between the gate electrode and the ferroelectric layer; and a second insertion layer, disposed between the ferroelectric layer and the channel layer, wherein the second insertion layer has a thickness less than a thickness of the first insertion layer.

Abstract: A device includes a first transistor over a substrate, a second transistor disposed over the first transistor, and a memory element disposed over the second transistor. The second transistor includes a channel layer, a gate dielectric layer surrounding a sidewall of the channel layer, and a gate electrode surrounding a sidewall of the gate dielectric layer.

Abstract: Buffing of a footwear component allows for an alteration of the component surface to achieve an intended surface for aesthetics and/or manufacturing purposes. The buffing is performed in a system having a vision module, a sidewall buffing module, an up surface buffing module, and a down surface buffing module. Each of the buffing modules are adapted for the unique shape and sizes of a footwear component to effectively and automatically buff the footwear component.

Abstract: A double side-scroll mouse device includes a housing unit, a main button unit, and a side scroll unit. The housing unit has a lower casing and a casing side skirt. The lower casing has spaced-apart first and second lateral face portions. The casing side skirt has a first operating wall extending upwardly from one of the first and second lateral face portions, and a second operating wall portion extending upwardly from the first operating wall portion. The side scroll unit includes a first scroll wheel member that is disposed on the first operating wall portion and that is rotatable about a first axis, and a second scroll wheel member that is disposed on the second operating wall portion and that is rotatable about a second axis being substantially perpendicular to the first axis.

Abstract: An underwater ultrasonic device includes a curvilinear ultrasonic transducer and a plurality of straight linear ultrasonic transducers. The straight linear ultrasonic transducers are disposed with respect to the curvilinear ultrasonic transducer. A first angle is included between the straight linear ultrasonic transducers. One of the curvilinear ultrasonic transducer and the straight linear ultrasonic transducer is configured to transmit a plurality of ultrasonic signals. Another one of the curvilinear ultrasonic transducer and the straight linear ultrasonic transducer is configured to receive a plurality of reflected signals of the ultrasonic signals.

Abstract: A semiconductor device includes an active layer having first and second active regions, first and second source electrodes, first and second drain electrodes, first and second gate electrodes, a first source metal layer, first and second drain metal layers, and a source pad electrically connected to the first source metal layer. The second drain metal layer is electrically connected to the second drain electrode and the first source metal layer. A projection of the second drain metal layer on the active layer forms a drain metal layer region. An projection of the source pad on the active layer forms a source pad region. An area of an overlapping region between the source pad region and the drain metal layer region is smaller than or equal to 40% of an area of the drain metal layer region.

Abstract: A transistor device having fin structures, source and drain terminals, channel layers and a gate structure is provided. The fin structures are disposed on a material layer. The fin structures are arranged in parallel and extending in a first direction. The source and drain terminals are disposed on the fin structures and the material layer and cover opposite ends of the fin structures. The channel layers are disposed respectively on the fin structures, and each channel layer extends between the source and drain terminals on the same fin structure. The gate structure is disposed on the channel layers and across the fin structures. The gate structure extends in a second direction perpendicular to the first direction. The materials of the channel layers include a transition metal and a chalcogenide, the source and drain terminals include a metallic material, and the channel layers are covalently bonded with the source and drain terminals.

Abstract: A smart ring includes an antenna chip and a metal ring used as an antenna, and the antenna chip is electrically connected to the metal ring to form an antenna circuit. The metal body of the smart ring is designed as a composition structure of the antenna circuit, that is, the antenna is integrated into the metal ring, the space for accommodating the antennas and the cost for additional physical antennas are saved, and the design flexibility and the competitiveness of the product are improved. Nickel-zinc ferrite is unnecessary, which can reduce the cost. The ring can keep the radiation characteristic of the circular antenna that is not susceptible to the interference from human body. The metal body of the ring is a metal structure, which can fulfill both of strength requirement and texture requirement of the structure, and at the same time has good antenna characteristics.

Abstract: The present invention discloses a metadata-based diagnosis and management system for cardiovascular and cerebrovascular diseases, which belongs to the field of cardiovascular and cerebrovascular systems and is used to resolve a problem that a rapid diagnosis and a preliminary diagnosis of cardiovascular and cerebrovascular diseases cannot be quickly implemented at community hospitals, clinics, and other places with limited medical facilities. The system includes a physical status monitoring module, a preliminary diagnosis module, an electrocardiogram comparison module, and a model building module.

Abstract: The present invention discloses a medical clinical data quality analysis system based on big data, which relates to the field of medical big data technologies. The present invention is used to solve the technical problems that multi-link classified acquisition cannot be carried out on medical behaviors, and the quality of clinical data cannot be analyzed and reflected at the front end, middle link, and tail end of management. In the present invention, authenticity data, compliance data, process data and conclusive data are comprehensively acquired in admission, hospitalization, and discharge links of medical clinical data quality management, which is conducive to implementing multi-link classified acquisition of clinical medical behaviors, thereby facilitating subsequent dynamic and orderly quality analysis and control of clinical data.

Abstract: A ferroelectric tunnel junction (FTJ) memory device includes a bottom electrode located over a substrate, a top electrode overlying the bottom electrode, and a ferroelectric tunnel junction memory element located between the bottom electrode and the top electrode. The ferroelectric tunnel junction memory element includes at least one ferroelectric material layer and at least one tunneling dielectric layer.

Abstract: An analog to digital converter includes voltage divider circuits, front-end circuits, at least one converter circuit, and a controller circuit. The voltage divider circuits are configured to divide an input signal to generate first signals, in which the first signals have different levels. The front-end circuits are configured to respectively sample the first signals to generate second signals. The at least one converter circuit is configured to generate at least one digital output according to the second signals and a reference voltage. The controller circuit is configured to determine a level of the input signal according to the at least one digital output and select one of the at least one digital output according to the level of the input signal.

Abstract: The present disclosure discloses a signal relay apparatus having frequency locking mechanism that includes a receiving circuit, a frequency generation circuit, a frequency tracking circuit and a transmission circuit. The receiving circuit receives a receiving signal to retrieve data included therein according a corresponding receiving frequency signal. The frequency generation circuit receives a source clock signal and generates a target frequency signal according to a conversion parameter. The frequency tracking circuit calculates a frequency difference between the receiving frequency signal and the target frequency signal to adjust the conversion parameter accordingly. The transmission circuit generates a transmission signal that includes the data according to the target frequency signal.