Patents by Inventor Chun Chieh

Chun Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240170296
    Abstract: A method for forming a semiconductor structure includes forming strip patterns over a semiconductor substrate, forming a hard mask layer over the strip patterns, and forming a patterned photoresist layer over the hard mask layer. The patterned photoresist layer has a plurality of first openings. The method also includes etching the hard mask layer using the patterned photoresist layer. Remaining portions of the hard mask layer form a plurality of pillar patterns that are separated from one another. The method also includes depositing a dielectric layer along the plurality of pillar patterns, etching the dielectric layer to form a plurality of second openings, removing the plurality of pillar patterns to form a plurality of third openings in the dielectric layer, and etching the strip patterns using the dielectric layer as a mask.
    Type: Application
    Filed: October 24, 2023
    Publication date: May 23, 2024
    Inventors: Hung-Jung YAN, Chun-Chieh WANG, Tzu-Ming OU YANG
  • Publication number: 20240165676
    Abstract: A removal method applied to an aluminum electrode sheet with an oxide layer, including a soaking step. The soaking step includes soaking the aluminum electrode sheet in an ionic liquid to remove the oxide layer, such that the aluminum electrode sheet has an exposed part of aluminum metal, and the soaking step is performed in a nitrogen atmosphere.
    Type: Application
    Filed: May 30, 2023
    Publication date: May 23, 2024
    Applicant: APh ePower Co., Ltd.
    Inventors: Jui-Hsuan Wu, Shih Po Ta Tsai, Chun-Chieh Yang, Shih-Min Chen
  • Patent number: 11991887
    Abstract: Three-dimensional memories are provided. A three-dimensional memory includes a memory cell array, a first interconnect structure, a bit line decoder and a second interconnect structure. The bit line decoder is formed under the memory cell array and the first interconnect structure. The memory cell array includes a plurality of memory cells formed in a plurality of levels stacked in a first direction. The first interconnect structure includes at least one bit line extending in a second direction that is perpendicular to the first direction. The bit line includes a plurality of sub-bit lines stacked in the first direction. Each of the sub-bit lines is coupled to the memory cells that are arranged in a line in the corresponding level of the memory cell array. The second interconnect structure is configured to connect the bit line to the bit line decoder passing through the first interconnect structure.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chenchen Jacob Wang, Chun-Chieh Lu, Yi-Ching Liu
  • Patent number: 11990493
    Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a front surface, a back surface opposite to the front surface, and a light-sensing region close to the front surface. The image sensor device includes an insulating layer covering the back surface and extending into the semiconductor substrate. The protection layer has a first refractive index, and the first refractive index is less than a second refractive index of the semiconductor substrate and greater than a third refractive index of the insulating layer, and the protection layer conformally and continuously covers the back surface and extends into the semiconductor substrate. The image sensor device includes a reflective structure surrounded by insulating layer in the semiconductor substrate.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chieh Fang, Ming-Chi Wu, Ji-Heng Jiang, Chi-Yuan Wen, Chien-Nan Tu, Yu-Lung Yeh, Shih-Shiung Chen, Kun-Yu Lin
  • Patent number: 11990550
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The semiconductor structure also includes a S/D silicide layer formed on the S/D epitaxial layer, and the S/D silicide layer has a first width, the S/D epitaxial layer has a second width, and the first width is smaller than the second width. The semiconductor structure includes a dielectric spacer between the gate structure and the S/D silicide layer, and a top surface of the dielectric spacer is lower than a top surface of the gate structure.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chieh Wang, Yu-Ting Lin, Yueh-Ching Pai, Shih-Chieh Chang, Huai-Tei Yang
  • Publication number: 20240161323
    Abstract: The present disclosure provides a component matching and reporting method, which includes steps as follows. A 3D file is parsed to obtain features; the features is analyzed according to a feature analysis parameter to find out at least one component feature; it is judged whether the at least one component feature corresponds to a component according to a feature judgment parameter; when the at least one component feature corresponds to the component, the component is located; after the component is located, the component is measured to output a measurement report.
    Type: Application
    Filed: February 18, 2023
    Publication date: May 16, 2024
    Inventors: Ke-Min HU, Trista Pei-Chun CHEN, Chun-Hung LIN, Chun Chieh CHEN
  • Publication number: 20240161818
    Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.
    Type: Application
    Filed: November 30, 2022
    Publication date: May 16, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hsien Huang, Yu-Tse Kuo, Shu-Ru Wang, Li-Ping Huang, Yu-Fang Chen, Chun-Yen Tseng, Tzu-Feng Chang, Chun-Chieh Chang
  • Publication number: 20240152288
    Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
    Type: Application
    Filed: January 15, 2024
    Publication date: May 9, 2024
    Applicant: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Chun-Chieh Kuo, Ching-Hui Lin, Yang-Chih Shen
  • Patent number: 11980026
    Abstract: A random code generating method for the magnetoresistive random access memory is provided. Firstly, a first magnetoresistive random access memory cell and a second magnetoresistive random access memory cell are programmed into an anti-parallel state. Then, an initial value of a control current is set. Then, an enroll action is performed on the first and second magnetoresistive random access memory cells. If the first and second magnetoresistive random access memory cells fail to pass the verification action, the control current is increased by a current increment, and the step of setting the control current is performed again. If the first and second magnetoresistive random access memory cells pass the verification action, a one-bit random code is stored in the first magnetoresistive random access memory cell or the second magnetoresistive random access memory cell.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: May 7, 2024
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Tsung-Mu Lai, Chun-Yuan Lo, Chun-Chieh Chao
  • Publication number: 20240145605
    Abstract: The present invention provides a manufacturing method of a photodiode structure. The method includes the following steps: providing a substrate; performing an epitaxial process to form a first semiconductor layer on the substrate; performing an active area patterning and etching process to form a recessed portion on the first semiconductor layer; performing a first coating process to form a first anti-reflection layer on the first semiconductor layer; and performing an ion implantation process to pass through the first anti-reflection layer and form a second semiconductor layer in the recessed portion.
    Type: Application
    Filed: October 26, 2023
    Publication date: May 2, 2024
    Inventor: Chun-Chieh LIN
  • Publication number: 20240138658
    Abstract: A medical visualisation device includes a main device part and the auxiliary component couplable to the main device part. The main device part includes an image sensor adapted to generate image data indicative of a view from the main device part, a light emitter adapted to provide illumination of the view, and a main coupling part having one or more main terminals electrically connected to the light emitter and the image sensor. The auxiliary component includes a device wireless communication module adapted to communicate with a monitor wireless communication module of a monitor device, the device wireless communication module being adapted to transmit encoded image data using a downstream data channel to the monitor wireless communication module.
    Type: Application
    Filed: March 1, 2022
    Publication date: May 2, 2024
    Applicant: AMBU A/S
    Inventors: Brian NIELSEN, Kasper Rieland JAKOBSEN, Chun-Chieh CHEN
  • Publication number: 20240141922
    Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Applicant: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Chun-Chieh Wang, Shu-Hao Kuo
  • Publication number: 20240130605
    Abstract: A medical visualisation system including a medical visualisation device having: an image sensor configured to generate image data, a light emitter, a device processing unit configured to receive the image data from the image sensor and encode the image data to provide encoded image data based on the image data, and a device wireless transceiver configured to communicate with a monitor wireless transceiver of a monitor device, the device wireless transceiver being configured to receive the encoded image data from the device processing unit and transmit the encoded image data using a downstream data channel from the device wireless transceiver to the monitor wireless transceiver and to receive settings data using an upstream data channel from the monitor wireless transceiver to the device wireless transceiver.
    Type: Application
    Filed: March 1, 2022
    Publication date: April 25, 2024
    Applicant: AMBU A/S
    Inventors: Brian NIELSEN, Kasper Rieland JAKOBSEN, Chun-Chieh CHEN
  • Publication number: 20240133467
    Abstract: A waterproof click pad device includes a click pad, a frame and a waterproof unit. The frame surrounds the click pad and surrounds an axis passing through the click pad. The waterproof unit is transverse to the axis and is in sheet form. The waterproof unit includes a frame adhesive member surrounding the axis and adhered to the frame, a first non-adhesive member surrounding the axis, connected to an inner periphery of the frame adhesive member and spaced apart from and located above the frame, a second non-adhesive member surrounding the axis, connected to an inner periphery of the first non-adhesive member and spaced apart from and located above the click pad and the frame, and an plate adhesive member connected to an inner periphery of the second non-adhesive member and adhered to the click pad.
    Type: Application
    Filed: January 4, 2023
    Publication date: April 25, 2024
    Applicant: SUNREX TECHNOLOGY CORP.
    Inventors: Yu-Xiang GENG, Chun-Chieh CHEN, Ling-Cheng TSENG, Yi-Wen TSAI, Ching-Yao HUANG
  • Publication number: 20240134807
    Abstract: The invention relates to a logic control device of a serial peripheral interface, a master-slave system and a master-slave switchover method therefor. The logic control device is connected between N masters and M slaves, and define master-slave connection relationships between each of the masters and each of the slaves. Each of the master-slave connection relationship is that each of the masters and each of the slaves transmit information one-to-one at the same time, and includes connecting the logic control device between the masters and the slaves to form the master-slave system as well as the master-slave switchover method therefor.
    Type: Application
    Filed: October 19, 2022
    Publication date: April 25, 2024
    Inventors: CHUN CHIEH WANG, CHENG YU WANG, JIN KAI YANG
  • Patent number: 11966374
    Abstract: The present invention discloses a medical clinical data quality analysis system based on big data, which relates to the field of medical big data technologies. The present invention is used to solve the technical problems that multi-link classified acquisition cannot be carried out on medical behaviors, and the quality of clinical data cannot be analyzed and reflected at the front end, middle link, and tail end of management. In the present invention, authenticity data, compliance data, process data and conclusive data are comprehensively acquired in admission, hospitalization, and discharge links of medical clinical data quality management, which is conducive to implementing multi-link classified acquisition of clinical medical behaviors, thereby facilitating subsequent dynamic and orderly quality analysis and control of clinical data.
    Type: Grant
    Filed: July 11, 2023
    Date of Patent: April 23, 2024
    Assignee: SERV MEDICAL PTE. LTD.
    Inventors: Chun-Chieh Hsu, Shiyu Zhang, Jiangjiu Huang, Yingxi Wang, Rashaad Nawaz Tawquir
  • Patent number: 11968914
    Abstract: A memory cell includes: a resistive material layer comprising a first portion that extends along a first direction and a second portion that extends along a second direction, wherein the first and second directions are different from each other; a first electrode coupled to a bottom surface of the first portion of the resistive material layer; and a second electrode coupled to the second portion of the resistive material layer.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Mo, Shih-Chi Kuo
  • Patent number: 11961745
    Abstract: The present disclosure describes an apparatus for processing one or more objects. The apparatus includes a carrier configured to hold the one or more objects, a tank filled with a processing agent and configured to receive the carrier, and a spinning portion configured to contact the one or more objects and to spin the one or more objects to disturb a flow field of the processing agent.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Yu Lin, Shih-Chi Kuo, Chun-Chieh Mo
  • Patent number: 11963368
    Abstract: A memory includes: a dielectric fin formed over a substrate; and a pair of memory cells disposed along respective sidewalls of the dielectric fin, each of the pair of memory cells comprising: a first conductor layer; a selector layer; a resistive material layer; and a second conductor layer, wherein the first conductor layer, selector layer, resistive material layer, and second conductor layer each includes upper and lower boundaries, and at least one of the upper and lower boundaries is tilted away from one of the sidewalls of the dielectric fin by an angle.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Mo, Shih-Chi Kuo, Tsai-Hao Hung
  • Patent number: D1026916
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: May 14, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Hao-Jen Fang, Kung-Ju Chen, Wei-Yi Chang, Chun-Chieh Chen, Chih-Wen Chiang, Sheng-Hung Lee